ADS1255ADS1256SBAS288C − JUNE 2003 − REVISED MARCH 2004Very Low Noise, 24ĆBitAnalogĆtoĆDigital ConverterFEATURESD24 Bits, No Missing CodesDESCRIPTIONThe ADS1255 and ADS1256 are extremely low-noise,24-bit analog-to-digital (A/D) converters. They providecomplete high-resolution measurement solutions for themost demanding applications.The converter is comprised of a 4th-order, delta-sigma(∆Σ) modulator followed by a programmable digital filter. Aflexible input multiplexer handles differential orsingle-ended signals and includes circuitry to verify theintegrity of the external sensor connected to the inputs.The selectable input buffer greatly increases the inputimpedance and the low-noise programmable gainamplifier (PGA) provides gains from 1 to in binary steps.The programmable filter allows the user to optimizebetween a resolution of up to 23 bits noise-free and a datarate of up to 30k samples per second (SPS). Theconverters offer fast channel cycling for measuringmultiplexed inputs and can also perform one-shotconversions that settle in just a single cycle.Communication is handled over an SPI-compatible serialinterface that can operate with a 2-wire connection.Onboard calibration supports both self and systemcorrection of offset and gain errors for all the PGA settings.Bidirectional digital I/Os and a programmable clock outputdriver are provided for general use. The ADS1255 ispackaged in an SSOP-20, and the ADS1256 in anSSOP-28.VREFPVREFNDVDDClockGeneratorMuxandSensorDetect1:BufferPGA4th−OrderModulatorProgrammableDigitalFilterControlRESETSYNC/PDWNDRDYGeneralPurposeDigitalI/OSerialInterfaceSCLKDINDOUTCSAGNDD3D2ADS1256OnlyD1D0/CLKOUTDGNDXTAL1/CLKINXTAL2DDDData Output Rates to 30kSPSDFast Channel Cycling− All Data Rates and PGA SettingsUp to 23 Bits Noise-Free Resolution±0.0010% Nonlinearity (max)− 18.6 Bits Noise-Free (21.3 Effective Bits)at 1.45kHzDOne-Shot Conversions with Single-CycleSettlingDFlexible Input Multiplexer with Sensor DetectDDDSelf and System Calibration for All PGASettings− Four Differential Inputs (ADS1256 only)− Eight Single-Ended Inputs (ADS1256 only)Chopper-Stabilized Input BufferLow-Noise PGA: 27nV Input-Referred NoiseDDDD5V Tolerant SPI-Compatible Serial InterfaceAnalog Supply: 5VDigital Supply: 1.8V to 3.6VPower Dissipation− As Low as 38mW in Normal Mode− 0.4mW in Standby ModeAVDDAIN0AIN1AIN2ADS1256OnlyAIN3AIN4AIN5AIN6AIN7AINCOMAPPLICATIONSDWeigh ScalesDScientific InstrumentationDIndustrial Process ControlDMedical EquipmentDTest and MeasurementPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. Productsconform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.Copyright 2003−2004, Texas Instruments Incorporatedwww.ti.comADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004ORDERING INFORMATION(1)PRODUCTADS1255ADS1256PACKAGE-LEADSSOP-20SSOP-28PACKAGEDESIGNATORDBDBPACKAGEMARKINGADS1255IDBADS1256IDBORDERING NUMBERADS1255IDBTADS1255IDBRADS1256IDBTADS1256IDBRTRANSPORT MEDIA,QUANTITYTape and Reel, 250Tape and Reel, 1000Tape and Reel, 250Tape and Reel, 1000(1)For the most current package and ordering information, refer to our web site at www.ti.com.This integrated circuit can be damaged by ESD. TexasInstruments recommends that all integrated circuits behandled with appropriate precautions. Failure to observeproper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation tocomplete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range unless otherwise noted(1)ADS1255, ADS1256AVDD to AGNDDVDD to DGNDAGND to DGNDInput CurrentAnalog inputs to AGNDDIN, SCLK, CS, RESET,SYNC/PDWN,XTAL1/CLKIN to DGNDD0/CLKOUT, D1, D2, D3to DGND−0.3 to +6−0.3 to +3.6−0.3 to +0.3100, Momentary10, Continuous−0.3 to AVDD + 0.3−0.3 to +6UNITVVVmAmAVVDigitalinputs−0.3 to DVDD + 0.3+150−40 to +105−60 to +150V°C°C°CMaximum Junction TemperatureOperating Temperature RangeStorage Temperature RangeLead Temperature (soldering, 10s)+300°C(1)Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure toabsolute maximum conditions for extended periods may degradedevice reliability. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyondthose specified is not implied.2ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004ELECTRICAL CHARACTERISTICS All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = +2.5V, unless otherwise noted.PARAMETERAnalog InputsFull-scale input voltage (AINP − AINN)Absolute input voltage(AIN0-7, AINCOM to AGND)Programmable gain amplifierBuffer off, PGA = 1, 2, 4, 8, 16Differential input impedanceBuffer off, PGA = 32, Buffer on, fDATA ≤ 50Hz(1)SDCS[1:0] = 01Sensor detect current sourcesSystem PerformanceResolutionNo missing codesData rate (fDATA)Integral nonlinearityOffset errorOffset driftGain errorGain driftCommon-mode rejectionNoiseAVDD power-supply rejectionDVDD power-supply rejectionVoltage Reference InputsReference input voltage (VREF)Negative reference input (VREFN)Positive reference input (VREFP)Voltage reference impedanceDigital Input/OutputVIHVILVOHVOLInput hysteresisInput leakageMaster clock rateDIN, SCLK, XTAL1/CLKIN,SYNC/PDWN, CS, RESETD0/CLKOUT, D1, D2, D3IOH = 5mAIOL = 5mA0 < VDIGITAL INPUT < DVDDExternal crystal between XTAL1 andXTAL2External oscillator driving CLKIN0.8 DVDD0.8 DVDDDGND0.8 DVDD0.2 DVDD0.5±1020.17.687.6810105.25DVDD0.2 DVDDVVVVVVµAMHzMHzVREF ≡ VREFP − VREFNBuffer offBuffer on(6)Buffer offBuffer on(6)fCLKIN = 7.68MHz0.5AGND − 0.1AGNDVREFN + 0.5VREFN + 0.5TEST CONDITIONSMINTYP±2VREF/PGAMAXUNITVBuffer offBuffer onAGND − 0.1AGND1150/PGA4.7800.521024AVDD + 0.1AVDD − 2.0VVkΩkΩMΩµAµAµABitSDCS[1:0] = 10SDCS[1:0] = 11All data rates and PGA settingsfCLKIN = 7.68MHzDifferential input, PGA = 1Differential input, PGA = After calibrationPGA = 1PGA = After calibration, PGA = 1, Buffer onAfter calibration, PGA = , Buffer onPGA = 1PGA = fCM(4) = 60Hz, fDATA = 30kSPS(5)±5% ∆ in AVDD±10% ∆ in DVDD242.5±0.0003±0.0007On the level of the noise±100±4±0.005±0.03±0.8±0.560110See Noise Performance Tables701002.52.6VREFP − 0.5VREFP − 0.530,000±0.0010BitSPS(2)%FSR(3)%FSRnV/°CnV/°C%%ppm/°Cppm/°CdBdBdBVVVVVkΩAVDD + 0.1AVDD − 2.018.53ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004ELECTRICAL CHARACTERISTICS (continued)All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = +2.5V, unless otherwise noted.PARAMETERPower-SupplyAVDDDVDDPower-down modeStandby modeAVDD currentNormal mode, PGA = 1, Buffer offNormal mode, PGA = , Buffer offNormal mode, PGA = 1, Buffer onNormal mode, PGA = , Buffer onPower-down modeDVDD currentStandby mode, CLKOUT off,DVDD = 3.3VNormal mode, CLKOUT off,DVDD = 3.3VPower dissipationTemperature RangeSpecifiedOperatingStorage−40−40−60+85+105+150°C°C°CNormal mode, PGA = 1, Buffer off,DVDD = 3.3VStandby mode, DVDD = 3.3V950.9380.42572071613361022195024.751.85.253.62VVµAµAmAmAmAmAµAµAmAmWmWTEST CONDITIONSMINTYPMAXUNIT(1)See text for more information on input impedance.(2)SPS = samples per second.(3)FSR = full-scale range = 4VREF/PGA.(4)fCM is the frequency of the common-mode input signal.(5)Placing a notch of the digital filter at 60Hz (setting fDATA = 60SPS, 30SPS, 15SPS, 10SPS, 5SPS, or 2.5SPS) will further improve thecommon-mode rejection of this frequency.(6)The reference input range with Buffer on is restricted only if self-calibration or gain self-calibration is to be used. If using system calibration orwriting calibration values directly to the registers, the entire Buffer off range can be used.4ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004PIN ASSIGNMENTSSSOP PACKAGE(TOP VIEW)AVDDAGNDVREFNVREFPAINCOMAIN0AIN1SYNC, PDWNRESET123456720D119D0/CLKOUT18SCLK17DINAVDDAGNDVREFNVREFPAINCOMAIN0AIN1AIN2AIN3123456728D327D226D125D0/CLKOUT24SCLK23DINADS125516DOUT15DRDY14CS13XTAL1/CLKIN12XTAL211DGNDADS125622DOUT21DRDY20CS19XTAL1/CLKIN18XTAL217DGND16DVDD15RESETAIN410AIN511AIN612AIN713SYNC, PDWN14DVDD10Terminal FunctionsTERMINAL NO.NAMEAVDDAGNDVREFNVREFPAINCOMAIN0AIN1AIN2AIN3AIN4AIN5AIN6AIN7SYNC/PDWNRESETDVDDDGNDXTAL2XTAL1/CLKINCSDRDYDOUTDINSCLKD0/CLKOUTD1D2ADS12551234567——————1011121314151617181920—ADS12561234567101112131415161718192021222324252627ANALOG/DIGITALINPUT/OUTPUTAnalogAnalogAnalog inputAnalog inputAnalog inputAnalog inputAnalog inputAnalog inputAnalog inputAnalog inputAnalog inputAnalog inputAnalog inputDigital input(1)(2): active lowDigital input(1)(2): active lowDigitalDigitalDigital(3)Digital/Digital input(2)Digital input(1)(2): active lowDigital output: active lowDigital outputDigital input(1)(2)Digital input(1)(2)Digital IO(4)Digital IO(4)Digital IO(4)DESCRIPTIONAnalog power supplyAnalog groundNegative reference inputPositive reference inputAnalog input commonAnalog input 0Analog input 1Analog input 2Analog input 3Analog input 4Analog input 5Analog input 6Analog input 7Synchronization / power down inputReset inputDigital power supplyDigital groundCrystal oscillator connectionCrystal oscillator connection / external clock inputChip selectData ready outputSerial data outputSerial data inputSerial clock inputDigital I/O 0 / clock outputDigital I/O 1Digital I/O 2Digital I/O 3D3—28Digital IO(4)(1)Schmitt-Trigger digital input.(2)5V tolerant digital input.(3)Leave disconnected if external clock input is applied to XTAL1/CLKIN.(4)Schmitt-Trigger digital input when the digital I/O is configured as an input.5ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004PARAMETER MEASUREMENT INFORMATIONCSt3SCLKt4DINt7DOUTt8t9t5t6t2Lt11t1t2Ht10Figure 1. Serial Interface TimingTIMING CHARACTERISTICS FOR FIGURE 1 SYMBOLt1t2Ht2Lt3t4t5t6t7t8t9t10DESCRIPTIONSCLK periodMIN4102009200050505050060RREG, WREG, RDATAt11Final SCLK falling edge of command to first SCLKrising edge of next command.RDATAC, RESET, SYNCRDATAC, STANDBY, SELFOCAL, SY-SOCAL, SELFGCAL,SYSGCAL, SELFCAL42410MAXUNITτCLKIN(1)τDATA(2)nsτDATAnsnsnsnsτCLKINnsnsτCLKINnsτCLKINτCLKINSCLK pulse width: highSCLK pulse width: lowCS low to first SCLK: setup time(3)Valid DIN to SCLK falling edge: setup timeValid DIN to SCLK falling edge: hold timeDelay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC,RREG CommandsSCLK rising edge to valid new DOUT: propagation delay(4)SCLK rising edge to DOUT invalid: hold timeLast SCLK falling edge to DOUT high impedanceNOTE: DOUT goes high impedance immediately when CS goes highCS low after final SCLK falling edgeWait for DRDY to go low(1)τCLKIN = master clock period = 1/fCLKIN.(2)τDATA = output data period 1/fDATA.(3)CS can be tied low.(4)DOUT load = 20pF 100kΩ to DGND.6ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004t13SCLKt12t14t15t13Figure 2. SCLK Reset TimingTIMING CHARACTERISTICS FOR FIGURE 2 SYMBOLt12t13t14t15DESCRIPTIONSCLK reset pattern, first high pulseSCLK reset pattern, low pulseSCLK reset pattern, second high pulseSCLK reset pattern, third high pulseMIN300555010507501250MAX500UNITτCLKIN(1)τCLKINτCLKINτCLKIN(1)τCLKIN = master clock period = 1/fCLKIN.t16RESET,SYNC/PDWNFigure 3. RESET and SYNC/PDWN TimingTIMING CHARACTERISTICS FOR FIGURE 3 SYMBOLt16DESCRIPTIONRESET, SYNC/PDWN, pulse widthMIN4MAXUNITτCLKIN(1)(1)τCLKIN = master clock period = 1/fCLKIN.t17DRDYFigure 4. DRDY Update TimingTIMING CHARACTERISTICS FOR FIGURE 4 SYMBOLt17DESCRIPTIONConversion data invalid while being updated (DRDY shown with no data retrieval)MIN16MAXUNITτCLKIN(1)(1)τCLKIN = master clock period = 1/fCLKIN.7ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004TYPICAL CHARACTERISTICSTA = +25°C, AVDD = 5V, DVDD = 1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = 2.5V, unless otherwise noted.OFFSETDRIFTHISTOGRAM25PGA=190Unitsfrom3ProductionLots3025PercentofPopulation20151050−500−450−400−350−300−250−200−150−100−50050100150200250300350400450500−20−18−16−14−12−10−8−6−4−202468101214161820OffsetDrift(nV/_C)GAINERRORHISTOGRAM25PGA=90Unitsfrom3ProductionLots20PercentofPopulation151052520PercentofPopulation15105000.10.20.30.40.50.60.70.80.91.01.11.21.31.41.51.61.71.81.92.0GainDrift(ppm/_C)00.10.20.30.40.50.60.70.80.91.01.11.21.31.41.51.61.71.81.92.0GainDrift(ppm/_C)−0.060−0.057−0.054−0.051−0.048−0.045−0.042−0.039−0.036−0.033−0.030−0.027−0.024−0.021−0.018−0.015−0.012−0.009−0.006−0.0030GainError(%)GAINDRIFTHISTOGRAMPGA=90Unitsfrom3ProductionLots0PGA=OFFSETDRIFTHISTOGRAM90Unitsfrom3ProductionLots20PercentofPopulation151050OffsetDrift(nV/_C)GAINERRORHISTOGRAM3025PercentofPopulation20151050PGA=190Unitsfrom3ProductionLots2520PercentofPopulation1510508−0.0100−0.0095−0.0090−0.0085−0.0080−0.0075−0.0070−0.0065−0.0060−0.0055−0.0050−0.0045−0.0040−0.0035−0.0030−0.0025−0.0020−0.0015−0.0010−0.00050GainError(%)GAINDRIFTHISTOGRAMPGA=190Unitsfrom3ProductionLotsADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004TYPICAL CHARACTERISTICS (continued)TA = +25°C, AVDD = 5V, DVDD = 1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = 2.5V, unless otherwise noted.NOISEHISTOGRAM100PGA=1DataRate=2.5SPS80PercentofPopulationPercentofPopulationBuffer=Off256Readings2025PGA=DataRate=2.5SPSBuffer=Off256ReadingsNOISEHISTOGRAM601540102050OutputCode(LSB)NOISEHISTOGRAM25PGA=1DataRate=1kSPS20PercentofPopulation15PercentofPopulationBuffer=Off4096Readings2025151010550−20−18−16−14−12−10−8−6−4−202468101214161820OutputCode(LSB)0−150−135−120−105−90−75−60−45−30−150153045607590105120135150OutputCode(LSB)NOISEHISTOGRAM25PGA=1DataRate=30kSPSBuffer=Off4096ReadingsPercentofPopulationPGA=DataRate=30kSPS20Buffer=Off4096Readings15105−600−540−480−420−360−300−240−180−120−60060120180240300360420480540600OutputCode(LSB)0−100−90−80−70−60−50−40−30−20−100102030405060708090100NOISEHISTOGRAM2520PercentofPopulation151050OutputCode(LSB)−20−18−16−14−12−10−8−6−4−202468101214161820OutputCode(LSB)NOISEHISTOGRAMPGA=DataRate=1kSPSBuffer=Off4096Readings−5−4−3−2−101234509ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004TYPICAL CHARACTERISTICS (continued)TA = +25°C, AVDD = 5V, DVDD = 1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = 2.5V, unless otherwise noted.EFFECTIVENUMBEROFBITSvsINPUTVOLTAGE23PGA=122ENOB(rms)DataRate=1kSPS22ENOB(rms)21DataRate=30kSPSPGA=1DataRate=1kSPSEFFECTIVENUMBEROFBITSvsTEMPERATURE2321DataRate=30kSPS202019191800.51.01.52.02.53.03.54.04.55.0InputVoltage,VIN(V)18−50−30−101030507090110Temperature(_C)INTEGRALNONLINEARITYvsINPUTSIGNAL0.00060.0004INL(%ofFSR)0.00020−0.0002−0.0004PGA=1INTEGRALNONLINEARITYvsPGA0.00090.0008INL(%ofFSR)−40_C+85_C+125_C0.00070.00060.00050.00040.00030.00020.0001+25_CBufferOffBufferOn−0.0006−5−4−3−2−101234501248PGASetting1632InputVoltage,VIN(V)ANALOGSUPPLYCURRENTvsTEMPERATURE504540AnalogCurrent(mA)35302520151050−50−30−101030507090110PGA=,BufferOffPGA=1,BufferOnPGA=1,BufferOffAnalogCurrent(mA)PGA=,BufferOn40353025201510501ANALOGSUPPLYCURRENTvsPGABufferOnBufferOff248PGASetting1632Temperature(_C)10ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004OVERVIEWThe ADS1255 and ADS1256 are very low-noise A/Dconverters. The ADS1255 supports one differential or twosingle-ended inputs and has two general-purpose digitalI/Os. The ADS1256 supports four differential or eightsingle-ended inputs and has four general-purpose digitalI/Os. Otherwise, the two units are identical and arereferred to together in this data sheet as the ADS1255/6.Figure 5 shows a block diagram of the ADS1256. Theinput multiplexer selects which input pins are connected tothe A/D converter. Selectable current sources within theinput multiplexer can check for open- or short-circuitconditions on the external sensor. A selectable onboardinput buffer greatly reduces the input circuitry loading byproviding up to 80MΩ of impedance. A low-noise PGAprovides a gain of 1, 2, 4, 8, 16, 32, or . The ADS1255/6converter is comprised of a 4th-order, delta-sigmamodulator followed by a programmable digital filter.The modulator measures the amplified differential inputsignal, VIN = (AINP – AINN), against the differentialreference, VREF=(VREFP−VREFN). The differentialreference is scaled internally by a factor of two so that thefull-scale input range is ±2VREF (for PGA = 1).The digital filter receives the modulator signal andprovides a low-noise digital output. The data rate of thefilter is programmable from 2.5SPS to 30kSPS and allowstradeoffs between resolution and speed.Communication is done over an SPI-compatible serialinterface with a set of simple commands providing control ofthe ADS1255/6. Onboard registers store the various settingsfor the input multiplexer, sensor detect current sources, inputbuffer enable, PGA setting, data rate, etc. Either an externalcrystal or clock oscillator can be used to provide the clocksource. General-purpose digital I/Os provide static read/writecontrol of up to four pins. One of the pins can also be usedto supply a programmable clock output.VREFPVREFNΣVREFAIN0AIN1AIN2ADS1256OnlyAIN3AIN4AIN5AIN6AIN7AINCOMGeneralPurposeDigitalI/OSPISerialInterfaceInputMultiplexerAINPandSensorAINNDetect22VREFPGA1:ΣVIN•PGA4th−OrderModulatorProgrammableDigitalFilterRESETSYNC/PDWNA/DConverterClockGeneratorXTAL1/CLKINXTAL2BufferControlDRDYSCLKDINDOUTCSD3D2ADS1256OnlyD1D0/CLKOUTFigure 5. Block Diagram11ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004NOISE PERFORMANCEThe ADS1255/6 offer outstanding noise performance thatcan be optimized by adjusting the data rate or PGA setting.As the averaging is increased by reducing the data rate,the noise drops correspondingly. The PGA reduces theinput-referred noise when measuring lower level signals.Table 1 through Table 6 summarize the typical noiseperformance with the inputs shorted externally. In all sixtables, the following conditions apply: T = +25°C,AVDD=5V, DVDD= 1.8V, VREF = 2.5V, and fCLKIN =7.68MHz. Table 1 to Table 3 reflect the device input bufferenabled. Table 1 shows the rms value of the input-referrednoise in volts. Table 2 shows the effective number of bitsof resolution (ENOB), using the noise data from Table 1.ENOB is defined as:Table 2. Effective Number of Bits (ENOB, rms)with Buffer OnDATARATE(SPS)2.55101525305060100500100020003750750015,00030,000PGA125.325.024.824.624.324.223.923.823.422.321.721.220.820.420.119.8224.924.824.524.224.023.823.623.423.021.921.320.920.520.119.719.5424.924.524.123.823.423.323.022.922.521.520.820.420.019.619.319.1824.424.023.523.223.022.822.522.422.020.920.219.719.419.018.718.51623.823.322.922.522.222.121.821.721.420.319.819.319.018.518.218.03223.022.722.321.821.521.521.121.020.819.619.218.818.417.917.717.422.221.821.321.020.720.520.320.219.818.718.317.917.417.016.716.5lnǒFSRńRMSNoiseǓENOB+ln(2)where FSR is the full-scale range. Table 3 shows thenoise-free bits of resolution. It is calculated with the sameformula as ENOB except the peak-to-peak noise value isused instead of rms noise. Table 4 through Table 6 showthe same noise data, but with the input buffer disabled.Table 3. Noise-Free Resolution (bits)with Buffer OnDATARATE(SPS)2.55101525305060100500100020003750750015,00030,000PGA123.022.322.322.021.721.821.321.320.920.119.018.518.117.717.317.1222.622.422.021.721.421.321.120.920.719.618.618.117.817.317.016.7422.121.921.621.321.120.820.420.520.219.118.117.817.316.916.516.4821.721.321.020.720.520.419.919.819.618.617.517.016.616.215.915.91621.320.720.420.119.719.819.419.319.118.017.216.616.215.815.515.43220.820.319.919.319.219.018.818.818.517.316.516.115.715.314.914.619.719.318.918.718.518.117.917.817.416.315.615.314.714.413.913.8Table 1. Input Referred Noise (µV, rms)with Buffer OnDATARATE(SPS)2.55101525305060100500100020003750750015,00030,000PGA10.2470.3010.3390.4010.4940.5330.6290.6920.8751.9462.9314.1735.3947.2499.07410.72820.1560.1750.2140.20.3050.3350.3930.4380.51.2501.12.53.4604.5935.9216.70540.0800.1020.1380.1690.2240.2450.2920.3210.4090.6301.3251.8272.3763.1493.9614.44680.0560.0760.1060.1260.1490.1760.2160.2330.3050.81.0701.4921.8652.4362.9843.280160.0430.0610.0820.1070.1340.1380.1680.1840.2290.4970.60.9431.2241.6912.1252.416320.0370.0450.0610.0850.1020.1040.1360.1460.1700.3900.5120.6920.9121.2341.5171.7850.0330.0440.0610.0730.0930.1060.1220.1310.1690.3670.4860.6540.9061.1871.5151.74212ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004Table 4. Input Referred Noise (µV, rms)with Buffer OffDATARATE(SPS)2.55101525305060100500100020003750750015,00030,000PGA10.2470.2750.3380.4010.4850.5590.40.6880.8151.9572.8034.0255.4137.0178.86210.34120.1490.1760.2010.2210.2790.3150.3900.4170.5301.1481.7972.4443.2504.1435.4326.13740.0970.1090.1290.1500.1770.2020.2380.2810.3600.7721.1911.6152.0612.7223.3783.87380.0580.0700.0840.1090.1360.1420.1870.2040.2330.5310.9401.3101.5781.9982.4112.775160.0360.0460.0630.0700.0930.1070.1290.1340.1690.3750.5180.7000.9141.2411.5691.805320.0310.0390.0480.0630.0760.0930.1080.1090.1230.2760.3920.5260.6930.9141.1491.3130.0270.0380.0470.0570.0760.0820.1030.1110.1220.2590.3650.4610.6250.8571.0511.211DATARATE(SPS)2.55101525305060100500100020003750750015,00030,000Table 6. Noise-Free Resolution (bits)with Buffer OffPGA123.022.422.322.021.821.621.321.221.120.019.018.518.117.717.417.1222.422.122.121.821.721.421.321.020.519.718.718.317.817.617.117.0422.021.921.721.421.121.120.720.620.319.318.417.917.517.016.816.6821.921.521.520.820.720.420.120.119.918.917.717.417.016.616.316.01621.321.220.820.620.320.019.819.819.518.317.517.016.716.215.915.63221.120.420.319.919.516.419.119.119.017.816.916.416.115.715.315.020.019.419.219.018.618.518.218.117.916.915.915.615.214.814.414.4Table 5. Effective Number of Bits (ENOB, rms)with Buffer OffDATARATE(SPS)2.55101525305060100500100020003750750015,00030,000PGA125.325.124.824.624.324.123.923.823.522.321.821.220.820.420.119.9225.024.824.624.424.123.923.623.523.222.121.421.020.620.219.819.24.624.524.224.023.823.623.323.122.721.621.020.620.219.819.519.3824.424.123.823.423.123.122.722.522.421.220.319.919.619.319.018.81624.023.723.223.122.722.522.222.121.820.720.219.819.418.918.618.43223.222.922.622.222.021.721.521.521.320.119.619.218.818.418.117.922.522.021.721.421.020.920.520.420.319.218.718.417.917.517.217.013ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004INPUT MULTIPLEXERFigure 6 shows a simplified diagram of the inputmultiplexer. This flexible block allows any analog input pinto be connected to either of the converter differentialinputs. That is, any pin can be selected as the positiveinput (AINP); likewise, any pin can be selected as thenegative input (AINN). The pin selection is controlled bythe multiplexer register.The ADS1256 offers nine analog inputs, which can beconfigured as four independent differential inputs, eightsingle-ended inputs, or a combination of differential andsingle-ended inputs.The ADS1255 offers three analog inputs, which can beconfigured as one differential input or two single-endedinputs. When using the ADS1255 and programming theinput, make sure to select only the available inputs whenprogramming the input multiplexer register.In general, there are no restrictions on input pin selection.However, for optimum analog performance, the followingrecommendations are made:1.For differential measurements use AIN0 throughAIN7, preferably adjacent inputs. For example, useAIN0 and AIN1. Do not use AINCOM.2.For single-ended measurements use AINCOM ascommon input and AIN0 through AIN7 assingle-ended inputs.3.Leave any unused analog inputs floating. Thisminimizes the input leakage current.ESD diodes protect the analog inputs. To keep thesediodes from turning on, make sure the voltages on theinput pins do not go below AGND by more than 100mV,and likewise do not exceed AVDD by more than 100mV:−100mV < (AIN0 − 7 and AINCOM) < AVDD + 100mV.When using ADS1255/6 for single-ended measurements,it is important to note that common input AINCOM does notneed to be tied to ground. For example, AINCOM can betied to a midpoint reference such as +2.5V or even AVDD.AVDDAIN0AVDDAIN1AVDDAVDDSensorDetectCurrentSourceAIN2AVDDAIN3AVDDAINPInputBufferAINNAIN4AVDDAIN5AVDDSensorDetectCurrentSourceAGNDAIN6AVDDAIN7ADS1256OnlyAINCOMInputMultiplexerAVDDAGNDFigure 6. Simplified Diagram of the Input Multiplexer14ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004OPEN/SHORT SENSOR DETECTIONThe sensor detect current sources (SDCS) provide ameans to verify the integrity of the external sensorconnected to the ADS1255/6. When enabled, the SDCSsupply a current (ISDC) of approximately 0.5µA, 2µA, or10µA to the sensor through the input multiplexer. TheSDCS bits in the ADCON register enable the SDCS andset the value of ISDC.When the SDCS are enabled, the ADS1255/6automatically turns on the analog input buffer regardlessof the BUFEN bit setting. This is done to prevent the inputcircuitry from loading the SDCS. AINP must stay below 3Vto be within the absolute input range of the buffer. Toensure this condition is met, a 3V clamp will start sinkingcurrent from AINP to AGND if AINP exceeds 3V. Note thatthis clamp is activated only when the SDCS are enabled.Figure 7 shows a simplified diagram of ADS1255/6 inputstructure with the external sensor modeled as resistanceRSENS between two input pins. When the SDCS areenabled, they source ISDC to the input pin connected toAINP and sink ISDC from the input pin connected to AINN.The two 25Ω series resistors, RMUX, model theADS1255/6 internal resistances. The signal measuredwith the SDCS enabled equals the total IR drop:ISDC×(2RMUX + RSENS). Note that when the sensor is adirect short (that is, RSENS = 0), there will still be a smallsignal measured by the ADS1255/6 when the SDCS areenabled: ISDC × 2RMUX.ANALOG INPUT BUFFERTo dramatically increase the input impedance presentedby the ADS1255/6, the low-drift chopper-stabilized buffercan be enabled via the BUFEN bit in the STATUS register.The input impedance with the buffer enabled can bemodeled by a resistor, as shown in Figure 8. Table 7 liststhe values of ZEFF for the different data rate settings. Theinput impedance scales inversely with the frequency ofCLKIN. For example, if fCLKIN is reduced by half to3.84MHz, ZEFF for a data rate of 50SPS will double from80MΩ to 160MΩ.AIN0AIN1AIN2ADS1256 OnlyAIN3AIN4AIN5AIN6AIN7AINCOMInputMultiplexerAINNAINPZEFFFigure 8. Effective Impedance with Buffer OnTable 7. Input Impedance with Buffer OnAVDDSensorDetectCurrentSourceDATA RATE(SPS)30,00015,0007,500ZEFF(MΩ)10101010102040404080RMUX25Ω3,750AINP3VClamp2,0001,000InputBuffer50010060≤ 50NOTE:fCLKIN = 7.68MHz.RSENSRMUX25ΩAINNSensorDetectCurrentSourceNOTE: Arrows indicate switch positions when the SDCS are enabled.Figure 7. Sensor Detect CircuitryWith the buffer enabled, the voltage on the analog inputswith respect to ground (listed in the ElectricalCharacteristics as “Absolute Input Voltage”) must remainbetween AGND and AVDD − 2.0V. Exceeding this rangereduces performance, in particular the linearity of theADS1255/6. This same voltage range, AGND toAVDD−2.0V, applies to the reference inputs whenperforming a self gain calibration with the buffer enabled.15ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004PROGRAMMABLE GAIN AMPLIFIER (PGA)The ADS1255/6 is a very high resolution converter. Tofurther complement its performance, the low-noise PGAprovides even more resolution when measuring smallerinput signals. For the best resolution, set the PGA to thehighest possible setting. This will depend on the largestinput signal to be measured. The ADS1255/6 full-scaleinput voltage equals ±2VREF/PGA. Table 8 shows thefull-scale input voltage for the different PGA settings forVREF = 2.5V. For example, if the largest signal to bemeasured is 1.0V, the optimum PGA setting would be 4,which gives a full-scale input voltage of 1.25V. HigherPGAs cannot be used since they cannot handle a 1.0Vinput signal.repeats with a period of τSAMPLE. This time is a function ofthe PGA setting as shown in Table 9 along with the valuesof the capacitor CA1 = CA2 = CA and CB.AVDD/2AIN0AIN1AIN2ADS1256 OnlyAIN3AIN4AIN5AIN6AIN7AINCOMAVDD/2InputMultiplexerAINNS2CA2AINPS1S1CBS2CA1Table 8. Full-Scale Input Voltage vsPGA SettingPGA SETTING12481632FULL-SCALE INPUT VOLTAGE (VREF = 2.5V)±5V±2.5V±1.25V±0.625V±312.5mV±156.25mV±78.125mVFigure 9. Simplified Input Structurewith Buffer OffτSAMPLEONS1OFFONS2OFFThe PGA is controlled by the ADCON register.Recalibrating the A/D converter after changing the PGAsetting is recommended. The time required forself-calibration is dependent on the PGA setting. See theCalibration section for more details. The analog currentand input impedance (when the buffer is disabled) vary asa function of PGA setting.Figure 10. S1 and S2 Switch Timing for Figure 9Table 9. Input Sampling Time, τSAMPLE, andCA and CB vs PGAPGASETTING12481632τSAMPLE(1)fCLKIN/4 (521ns)fCLKIN/4 (521ns)fCLKIN/4 (521ns)fCLKIN/4 (521ns)fCLKIN/4 (521ns)fCLKIN/2 (260ns)fCLKIN/2 (260ns)CA2.1pF4.2pF8.3pF17pF33pF33pF33pFCB2.4pF4.9pF9.7pF19pF39pF39pF39pFMODULATOR INPUT CIRCUITRYThe ADS1255/6 modulator measures the input signalusing internal capacitors that are continuously chargedand discharged. Figure 9 shows a simplified schematic ofthe ADS1255/6 input circuitry with the input bufferdisabled. Figure 10 shows the on/off timings of theswitches of Figure 9. S1 switches close during the inputsampling phase. With S1 closed, CA1 charges to AINP, CA2charges to AINN, and CB charges to (AINP – AINN). For thedischarge phase, S1 opens first and then S2 closes. CA1and CA2 discharge to approximately AVDD/2 and CBdischarges to 0V. This two-phase sample/discharge cycle(1)τSAMPLE for fCLKIN = 7.68MHz.16ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004The charging of the input capacitors draws a transientcurrent from the sensor driving the ADS1255/6 inputs. Theaverage value of this current can be used to calculate aneffective impedance ZEFF where ZEFF=VIN / IAVERAGE.Figure 11 shows the input circuitry with the capacitors andswitches of Figure 9 replaced by their effectiveimpedances. These impedances scale inversely with theCLKIN frequency. For example, if fCLKIN is reduced by afactor of two, the impedances will double. They alsochange with the PGA setting. Table 10 lists the effectiveimpedances with the buffer off for fCLKIN=7.68MHz.VREFPVREFNAVDDAVDDESDProtectionSelfGainCalibrationZEFF=18.5kΩ(1)AIN0AIN1AIN2ADS1256 OnlyAIN3AIN4AIN5AIN6AIN7AINCOMAINPInputMultiplexerAINNAVDD/2ZeffA=τSAMPLE/CA(1)fCLKIN=7.68MHzAINPAINNZeffB=τSAMPLE/CBZeffA=τSAMPLE/CAAVDD/2Figure 12. Simplified Reference Input CircuitryESD diodes protect the reference inputs. To keep thesediodes from turning on, make sure the voltages on thereference pins do not go below AGND by more than100mV, and likewise do not exceed AVDD by 100mV:Figure 11. Analog Input Effective Impedanceswith Buffer OffTable 10. Analog Input Impedances with Buffer OffPGASETTING124 81632NOTE:fCLKIN = 7.68MHz.ZeffA(kΩ)26013065331688ZeffB(kΩ)22011055281477−100mV < (VREFP or VREFN) < AVDD + 100mVDuring self gain calibration, all the switches in the inputmultiplexer are opened, VREFN is internally connected toAINN, and VREFP is connected to AINP. The input buffermay be disabled or enabled during calibration. When thebuffer is disabled, the reference pins will be driving thecircuitry shown in Figure 9 during self gain calibration,resulting in increased loading. To prevent this additionalloading from introducing gain errors, make sure thecircuitry driving the reference pins has adequate drivecapability. When the buffer is enabled, the loading on thereference pins will be much less, but the buffer will limit theallowable voltage range on VREFP and VREFN duringself or self gain calibration as the reference pins mustremain within the specified input range of the buffer inorder to establish proper gain calibration.A high-quality reference voltage is essential for achievingthe best performance from the ADS1255/6. Noise and drifton the reference degrade overall system performance. Itis especially critical that special care be given to thecircuitry generating the reference voltages and their layoutwhen operating in the low-noise settings (that is, with lowdata rates) to prevent the voltage reference from limitingperformance.VOLTAGE REFERENCE INPUTS (VREFP, VREFN)The voltage reference for the ADS1255/6 A/D converter isthe differential voltage between VREFP and VREFN:VREF = VREFP − VREFN. The reference inputs use astructure similar to that of the analog inputs with thecircuitry on the reference inputs of Figure 12. The loadpresented by the switched capacitor can be modeled withan effective impedance (ZEFF) of 18.5kΩ forfCLKIN=7.68MHz. The temperature coefficient of theeffective impedance of the voltage reference inputs isapproximately 35ppm/°C.17ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004DIGITAL FILTERThe programmable low-pass digital filter receives themodulator output and produces a high-resolution digitaloutput. By adjusting the amount of filtering, tradeoffs canbe made between resolution and data rate: filter more forhigher resolution, filter less for higher data rate. The filteris comprised of two sections, a fixed filter followed by aprogrammable filter. Figure 13 shows the block diagram ofthe analog modulator and digital filter. Data is supplied tothe filter from the analog modulator at a rate of fCLKIN/4.The fixed filter is a 5th-order sinc filter with a decimationvalue of that outputs data at a rate of fCLKIN/256. Thesecond stage of the filter is a programmable averager(1st-order sinc filter) with the number of averages set bythe DRATE register. The data rate is a function of thenumber of averages (Num_Ave) and is given byEquation1.Table 11 shows the averaging and corresponding data ratefor each of the 16 valid DRATE register settings whenfCLKIN= 7.68MHz. Note that the data rate scales directlywith the CLKIN frequency. For example, reducing fCLKINfrom 7.68MHz to 3.84MHz reduces the data rate forDR[7:0]=11110000 from 30,000SPS to 15,000SPS.Table 11. Number of Averages and Data Rate forEach Valid DRATE Register SettingDRATEDR[7:0]1111000011100000110100001100000010110000NUMBER OF AVERAGES FORPROGRAMMABLE FILTER(Num_Ave)1 (averager bypassed)2481530603005006001000120020003000600012,000DATA RATE(1)(SPS)30,00015,000750037502000100050010060503025151052.5fDataRate+CLKIN256ǒǓǒfCLKIN2561Num_AveǓ1Num_Ave(1)10100001100100101000001001110010Modulator Rate =fCLKIN/4DataRate+DataRate+ǒǓǒfCLKIN256Ǔ011000110101001101000011AnalogModulatorsinc5FilterProgrammableAverager0011001100100011Num_Ave(set by DRATE)Digital Filter0001001100000011(1)for fCLKIN = 7.68MHz.Figure 13. Block Diagram of the AnalogModulator and Digital Filter18ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004FREQUENCY RESPONSEThe low-pass digital filter sets the overall frequencyresponse for the ADS1255/6. The filter response is theproduct of the responses of the fixed and programmablefilter sections and is given by Equation 2.0−6−12−18Gain(dB)−24−30−36−42−48−54−60051015202530354045505560fDATA=2.5SPS·ŤH(f)Ť+Ǔȧȧsinǒ·Ǔȧȧsinǒ·ȧȧȧȧȧ·sinǒ·Ǔȧ·ȧNum_Ave·sinǒ·Ǔȧȧȧȧȧ|H(f)|+ŤHsinc5(f)Ť5256pffCLKIN4pfAverager256pNum_AveffCLKINfCLKIN256pffCLKIN(2)The digital filter attenuates noise on the modulator output,including noise from within the ADS1255/6 and externalnoise present on the ADS1255/6 input signal. Adjustingthe filtering by changing the number of averages used inthe programmable filter changes the filter bandwidth. Witha higher number of averages, bandwidth is reduced andmore noise is attenuated.The low-pass filter has notches (or zeros) at the dataoutput rate and multiples thereof. At these frequencies, thefilter has zero gain. This feature can be useful when tryingto eliminate a particular interference signal. For example,to eliminate 60Hz (and the harmonics) pickup, set the datarate equal to 2.5SPS, 5SPS, 10SPS, 15SPS, 30SPS, or60SPS. To help illustrate the filter characteristics,Figure 14 and Figure 15 show the responses at the datarate extremes of 30kSPS and 2.5SPS respectively.Table 12 summarizes the first-notch frequency and −3dBbandwidth for the different data rate settings.Frequency(Hz)Figure 15. Frequency Response forData Rate = 2.5SPSTable 12. First Notch Frequency and−3dB Filter BandwidthDATA RATE(SPS)30,00015,000750037502000100050010060(1)50(2)30(1)FIRST NOTCH(Hz)30,00015,000750037502000100050010060503025151052.5−3dB BANDWIDTH(Hz)6108073003161587844122144.226.522.113.311.16.634.422.211.10−20−40Gain(dB)−60−80−100−120−1400153045607590105120Frequency(kHz)fDATA=30kSPS25(2)15(1)10(3)5(3)2.5(3)NOTE:fCLKIN = 7.68MHz.(1)Notch at 60Hz.(2)Notch at 50Hz.(3)Notch at 50Hz and 60Hz.Figure 14. Frequency Response for Data Rate = 30kSPSThe digital filter low-pass characteristic repeats atmultiples of the modulator rate of fCLKIN/4. Figure 16 andFigure 17 show the responses plotted out to 7.68MHz atthe data rate extremes of 30kSPS and 2.5SPS. Noticehow the responses near DC, 1.92MHz, 3.84MHz,19ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 20045.76MHz, 7.68MHz, are the same. The digital filter willattenuate high-frequency noise on the ADS1255/6 inputsup to the frequency where the response repeats. Ifsignificant noise on the inputs is present above thisfrequency, make sure to remove with external filtering.Fortunately, this can be done on the ADS1255/6 with asimple RC filter, as shown in the Applications Section (seeFigure 25).Table 13. Settling Time vs Data RateDATA RATE(SPS)30,00015,0007500375020001000SETTLING TIME (t18)(ms)0.220.250.320.450.691.192.1910.1916.8520.1933.5240.1966.85100.19200.19400.190−20−40Gain(dB)−60−80−100−120−14001.923.84Frequency(MHz)fDATA=30kSPSfCLKIN50010060503025151052.5=7.68MHz5.767.68NOTE:fCLKIN = 7.68MHz.Settling Time Using SynchronizationFigure 16. Frequency Response Out to 7.68MHzfor Data Rate = 30kSPSThe SYNC/PDWN pin allows direct control of conversiontiming. Simply issue a Sync command or strobe theSYNC/PDWN pin after changing the analog inputs (seethe Synchronization section for more information). Theconversion begins when SYNC/PDWN is taken high,stopping the current conversion and restarting the digitalfilter. As soon as SYNC/PDWN goes low, the DRDYoutput goes high and remains high during the conversion.After the settling time (t18), DRDY goes low, indicating thatdata is available. The ADS1255/6 settles in a singlecycle—there is no need to ignore or discard data aftersynchronization. Figure 18 shows the data retrievalsequence following synchronization.0fDATA=2.5SPS−20−40Gain(dB)−60−80−100−120−14001.923.84Frequency(MHz)fCLKIN=7.68MHz5.767.68AINP−AINNSYNC/PDWNFigure 17. Frequency Response Out to 7.68MHzfor Data Rate = 2.5SPSDRDYt18SETTLING TIMEThe ADS1255/6 features a digital filter optimized for fastsettling. The settling time (time required for a step changeon the analog inputs to propagate through the filter) for thedifferent data rates is shown in Table 13. The followingsections highlight the single-cycle settling ability of thefilter and show various ways to control the conversionprocess.20DINDOUTRDATASettledDataFigure 18. Data Retrieval After SynchronizationADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004Settling Time Using the Input MultiplexerThe most efficient way to cycle through the inputs is tochange the multiplexer setting (using a WREG commandto the multiplexer register MUX) immediately after DRDYgoes low. Then, after changing the multiplexer, restart theconversion process by issuing the SYNC and WAKEUPcommands, and retrieve the data with the RDATAcommand. Changing the multiplexer before reading thedata allows the ADS1256 to start measuring the new inputchannel sooner. Figure 19 demonstrates efficient inputcycling. There is no need to ignore or discard data whilecycling through the channels of the input multiplexerbecause the ADS1256 fully settles before DRDY goes low,indicating data is ready.Step 1: When DRDY goes low, indicating that data is readyfor retrieval, update the multiplexer register MUX using theWREG command. For example, setting MUX to 23h givesAINP = AIN2, AINN = AIN3.Step 2: Restart the conversion process by issuing a SYNCcommand immediately followed by a WAKEUP command.Make sure to follow timing specification t11 betweencommands.Step 3: Read the data from the previous conversion usingthe RDATA command.Step 4: When DRDY goes low again, repeat the cycle byfirst updating the multiplexer register, then reading theprevious data.Table 14 gives the effective overall throughput (1/t19) whencycling the input multiplexer. The values for throughput(1/t19) assume the multiplexer was changed with a 3-byteWREG command and fSCLK = fCLKIN/4.Table 14. Multiplexer Cycling ThroughputDATA RATE(SPS)30,00015,000750037502000100050010060503025151052.5NOTE:fCLKIN = 7.68MHz.CYCLING THROUGHPUT (1/t19)(Hz)437438173043216514388374569859503025151052.5t19DRDYt20DINWREG23htoMUXregSYNCWAKEUPRDATAWREG45htoMUXregDatafromMUX=01hSYNCWAKEUPRDATADOUTDatafromMUX=23h01hMUXRegisterAINP=AIN0,AINN=AIN123hAINP=AIN2,AINN=AIN345hAINP=AIN4,AINN=AIN5Figure 19. Cycling the ADS1256 Input Multiplexer21ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004Settling Time Using One-Shot ModeA dramatic reduction in power consumption can be achievedin the ADS1255/6 by performing one-shot conversions usingthe STANDBY command; the sequence for this is shown inFigure 20. Issue the WAKEUP command from Standbymode to begin a one-shot conversion. Following the settlingtime (t18), DRDY will go low, indicating that the conversion iscomplete and data can be read using the RDATA command.The ADs1255/6 settles in a single cycle—there is no need toignore or discard data. Following the data read cycle, issueanother STANDBY command to reduce power consumption.When ready for the next measurement, repeat the cyclestarting with another WAKEUP command.the previous and current input signal and should thereforebe discarded. Figure 21 shows an example of readback inthis situation.Table 15. Data Settling Delay vs Data RateDATA RATE(SPS)30,00015,000750037502000100050010060503025151052.5SETTLING TIME(DRDY Periods)5321111111111111Settling Time while Continuously ConvertingAfter a synchronization, input multiplexer change, orwakeup from Standby mode, the ADS1255/6 willcontinuously convert the analog input. The conversionscoincide with the falling edge of DRDY. While continuouslyconverting, it is often more convenient to consider settlingtimes in terms of DRDY periods, as shown in Table 15.The DRDY period equals the inverse of the data rate.If there is a step change on the input signal whilecontinuously converting, performing a synchronizationoperation to start a new conversion is recommended.Otherwise, the next data will represent a combination ofADS1255/6StatusStandbyModet18PerformingOne−ShotConversionStandbyModeDRDYDINSTANDBYWAKEUPRDATASettledDataSTANDBYDOUTFigure 20. One-Shot Conversions Using the STANDBY CommandNewVINVIN=AINP−AINNOldVINOldVINDataMixofOldandNewVINDataDRDYDINDOUTFullySettledNewVINDataRDATASettledDataFigure 21. Step Change on VIN while Continuously Converting for Data Rates ≤ 3750SPS22ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004DATA FORMATThe ADS1255/6 output 24 bits of data in Binary Two’sComplement format. The LSB has a weight of2VREF/(PGA(223 − 1)). A positive full-scale input producesan output code of 7FFFFFh and the negative full-scaleinput produces an output code of 800000h. The outputclips at these codes for signals exceeding full-scale.Table 16 summarizes the ideal output codes for differentinput signals.CLOCK OUTPUT (D0/CLKOUT)The clock output pin can be used to clock another device,such as a microcontroller. This clock can be configured tooperate at frequencies of fCLKIN, fCLKIN/2, or fCLKIN/4 usingCLK1 and CLK0 in the ADCON register. Note that enablingthe output clock and driving an external load will increasethe digital power dissipation. Standby mode does notaffect the clock output status. That is, if Standby isenabled, the clock output will continue to run duringStandby mode. If the clock output function is not needed,it should be disabled by writing to the ADCON register afterpower-up or reset.Table 16. Ideal Output Code vs Input SignalINPUT SIGNAL VIN(AINP − AINN)IDEAL OUTPUT CODE(1)7FFFFFhCLOCK GENERATIONThe master clock source for the ADS1255/6 can beprovided using an external crystal or clock generator.When the clock is generated using a crystal, externalcapacitors must be provided to ensure start-up and astable clock frequency, as shown in Figure 22. Table 17lists two recommended crystals. Long leads should beminimized with the crystal placed close to the ADS1255/6pins. For information on ceramic resonators, seeapplication note SBAA104, Using Ceramic Resonatorswith the ADS1255/6, available for download atwww.ti.com.w)2VREFPGA)2VREFPGA(223*1)0000001h000000hFFFFFFh*2VREFPGA(223*1)v*2VREF223PGA223*1ǒǓ800000h(1)Excludes effects of noise, INL, offset, and gain errors.GENERAL-PURPOSE DIGITAL I/O (D0-D3)The ADS1256 has 4 pins dedicated for digital I/O and theADS1255 has 2 digital I/O pins. All of the digital I/O pins areindividually configurable as either inputs or outputsthrough the IO register. The DIR bits of the IO registerdefine whether each pin is an input or output, and the DIObits control the status of the pins. Reading back the DIOregister shows the state of the digital I/O pins, whether theyare configured as inputs or outputs by the DIR bits. Whendigital I/O pins are configured as inputs, the DIO registeris used to read the state of these pins. When configured asoutputs, DIO sets the output value. On the ADS1255, thedigital I/O pins D2 and D3 do not exist and the settings ofthe IO register bits that control operation of D2 and D3have no effect on that device.During Standby and Power-Down modes, the GPIOremain active. If configured as outputs, they continue todrive the pins. If configured as inputs, they must be driven(not left floating) to prevent excess power dissipation.The digital I/O pins are set as inputs after power-up or areset, except for D0/CLKOUT, which is enabled as a clockoutput. If the digital I/O pins are not used, either leave themas inputs tied to ground or configure them as outputs. Thisprevents excess power dissipation.CrystalC1XTAL1/CLKINC2XTAL2C1,C2:5pFto20pFFigure 22. Crystal ConnectionTable 17. Recommended CrystalsMANUFACTURERCitizenECSFREQUENCY7.68MHz8.0MHzPARTNUMBERCIA/53383ECS-80-5-4When using a crystal, neither the XTAL1/CLKIN norXTAL2 pins can be used to drive any other logic. If otherdevices need a clock source, the D0/CLKOUT pin isavailable for this function. When using an external clockgenerator, supply the clock signal to XTAL1/CLKIN andleave XTAL2 floating. Make sure the external clockgenerator supplies a clean clock waveform. Overshootand glitches on the clock will degrade overall performance.23ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004CALIBRATIONOffset and gain errors can be minimized using theADS1255/6 onboard calibration circuitry. Figure 23 showsthe calibration block diagram. Offset errors are correctedwith the Offset Calibration (OFC) register and, likewise,full-scale errors are corrected with the Full-ScaleCalibration (FSC) register. Each of these registers is24-bits and can be read from or written to.Output+·VǒPGA2VREFIN*OFCaFSCǓ·b(3)where α and β vary with data rate settings shown inTable 18 along with the ideal values (assumes perfectanalog performance) for OFC and FSC. OFC is a BinaryTwo’s Complement number that can range from−8,388,608 to 8,388,607, while FSC is unipolar rangingfrom 0 to 16,777,215.The ADS1255/6 supports both self-calibration and systemcalibration for any PGA setting using a set of fivecommands: SELFOCAL, SELFGCAL, SELFCAL,SYSOCAL, and SYSGCAL. Calibration can be done atany time, though in many applications the ADS1255/6 driftperformance is low enough that a single calibration is allthat is needed. DRDY goes high when calibration beginsand remains so until settled data is ready afterwards.There is no need to discard data after a calibration. It isstrongly recommended to issue a self-calibrationcommand after power-up when the reference hasstabilized. After a reset, the ADS1255/6 performsself-calibration. Calibration must be performed wheneverthe data rate changes and should be performed when thebuffer configuration or PGA changes.VREFPVREFNAINPPGAAINNAnalogModulatorDigitalFilterΣXOutputOFCRegisterFSCRegisterFigure 23. Calibration Block DiagramThe output of the ADS1255/6 after calibration is shown inEquation 3.Table 18. Calibration Values for Different Data Rate SettingsDATA RATE(SPS)30,00015,000750037502000100050010060503025151052.5α400000H400000H400000H400000H3C0000H3C0000H3C0000H4B0000H3E8000H4B0000H3E8000H4B0000H3E8000H5DC000H5DC000H5DC000Hβ1.86391.86391.86391.86391.74741.74741.74742.18431.82022.18431.82022.18431.82022.73042.73042.7304IDEAL OFC000000H000000H000000H000000H000000H000000H000000H000000H000000H000000H000000H000000H000000H000000H000000H000000HIDEAL FSC44AC08H44AC08H44AC08H44AC08H494008H494008H494008H3A99A0H4651F3H3A99A0H4651F3H3A99A0H4651F3H2EE14CH2EE14CH2EE14CH24ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004Self-CalibrationSelf-calibration corrects internal offset and gain errors.During self-calibration, the appropriate calibration signalsare applied internally to the analog inputs.SELFOCAL performs a self offset calibration. The analoginputs AINP and AINN are disconnected from the signalsource and connected to AVDD/2. See Table 19 for thetime required for self offset calibration for the different datarate settings. As with most of the ADS1255/6 timings, thecalibration time scales directly with fCLKIN. Self offsetcalibration updates the OFC register.Table 20. Self Gain Calibration TimingDATA RATE(SPS)30,00015,000750037502000100050010060503025151052.5NOTE:For fCLKIN = 7.68MHz.1417µs484µs617µs2417µs484µs617µsPGA SETTING48451µs484µs617µs8841.4ms2.4ms4.5ms21.0ms34.1ms41.7ms67.8ms83.0ms135.3ms207.0ms413.7ms827.0ms517µs551µs617µs16, 32, 651µs551µs751µsTable 19. Self Offset and System OffsetCalibration TimingDATA RATE(SPS)30,00015,000750037502000100050010060503025151052.5NOTE:For fCLKIN = 7.68MHz.SELF OFFSET CALIBRATION ANDSYSTEM OFFSET CALIBRATION TIME387µs453µs587µs853µs1.3ms2.3ms4.3ms20.3ms33.7ms40.3ms67.0ms80.3ms133.7ms200.3ms400.3ms800.3msSELFCAL performs first a self offset and then a self gaincalibration. The analog inputs are disconnected from thefrom the signal source during self-calibration. When usingthe input buffer with self-calibration, make sure to observethe common-mode range of the reference inputs asdescribed above. Table 21 shows the time required forself-calibration for the different data rate settings.Self-calibration updates both the OFC and FSC registers.Table 21. Self-Calibration TimingDATA RATE(SPS)30,00015,000750037502000100050010060503025151052.5NOTE:For fCLKIN = 7.68MHz.251596µs696µs6µs2596µs696µs6µsPGA SETTING48692µs696µs6µs1.3ms2.0ms3.6ms6.6ms31.2ms50.9ms61.8ms101.3ms123.2ms202.1ms307.2ms613.8ms1227.2ms696µs762µs6µs16, 32, 2µs6µs1029µsSELFGCAL performs a self gain calibration. The analoginputs AINP and AINN are disconnected from the signalsource and AINP is connected internally to VREFP whileAINN is connected to VREFN. Self gain calibration can beused with any PGA setting, and the ADS1255/6 hasexcellent gain calibration even for the higher PGA settings,as shown in the Typical Characteristics section. Using thebuffer will limit the common-mode range of the referenceinputs during self gain calibration since they will beconnected to the buffer inputs and must be within thespecified analog input range. When the voltage on VREFPor VREFN exceeds the buffer analog input range(AVDD– 2.0V), the buffer must be turned off during selfgain calibration. Otherwise, use system gain calibration orwrite the gain coefficients directly to the FSC register.Table 20 shows the time required for self gain calibrationfor the different data rate and PGA settings. Self gaincalibration updates the FSC register.ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004System CalibrationSystem calibration corrects both internal and externaloffset and gain errors using the SYSOCAL and SYSGCALcommands. During system calibration, the appropriatecalibration signals must be applied by the user to theinputs.SYSOCAL performs a system offset calibration. The usermust supply a zero input differential signal. TheADS1255/6 then computes a value that will nullify theoffset in the system. Table 22 shows the time required forsystem offset calibration for the different data rate settings.Note this timing is the same for the self offset calibration.System offset calibration updates the OFC register.SYSGCAL performs a system gain calibration. The usermust supply a full-scale input signal to the ADS1255/6.The ADS1255/6 then computes a value to nullify the gainerror in the system. System gain calibration can correctinputs that are 80% of the full-scale input voltage andlarger. Make sure not to exceed the full-scale input voltagewhen using system gain calibration. Table 22 shows thetime required for system gain calibration for the differentdata rate settings. System gain calibration updates theFSC register.SERIAL INTERFACEThe SPI-compatible serial interface consists of foursignals: CS, SCLK, DIN, and DOUT, and allows acontroller to communicate with the ADS1255/6. Theprogrammable functions are controlled using a set ofon-chip registers. Data is written to and read from theseregisters via the serial interfaceThe DRDY output line is used as a status signal to indicatewhen a conversion has been completed. DRDY goes lowwhen new data is available. The Timing Specificationshows the timing diagram for interfacing to theADS1255/6.CHIP SELECT (CS)The chip select (CS) input allows individual selection of aADS1255/6 device when multiple devices share the serialbus. CS must remain low for the duration of the serialcommunication. When CS is taken high, the serialinterface is reset and DOUT enters a high impedancestate. CS may be permanently tied low.SERIAL CLOCK (SCLK)The serial clock (SCLK) features a Schmitt-triggered inputand is used to clock data on the DIN and DOUT pins intoand out of the ADS1255/6. Even though the input hashysteresis, it is recommended to keep SCLK as clean aspossible to prevent glitches from accidentally shifting thedata. If SCLK is held low for 32 DRDY periods, the serialinterface will reset and the next SCLK pulse will start a newcommunication cycle. This timeout feature can be used torecover communication when a serial interface transmis-sion is interrupted. A special pattern on SCLK will reset thechip; see the RESET section for more details on thisprocedure.Table 22. System Gain Calibration TimingDATA RATE(SPS)30,00015,000750037502000100050010060503025151052.5NOTE:For fCLKIN = 7.68MHz.SYSTEM GAIN CALIBRATION TIME417µs484µs617µs884µs1.4ms2.4ms4.4ms20.4ms33.7ms40.4ms67.0ms80.4ms133.7ms200.4ms400.4ms800.4msDATA INPUT (DIN) AND DATA OUTPUT (DOUT)The data input pin (DIN) is used along with SCLK to senddata to the ADS1255/6. The data output pin (DOUT) alongwith SCLK is used to read data from the ADS1255/6. Dataon DIN is shifted into the part on the falling edge of SCLKwhile data is shifted out on DOUT on the rising edge ofSCLK. DOUT is high impedance when not in use to allowDIN and DOUT to be connected together and be driven bya bi-directional bus. Note: the RDATAC command mustnot be issued while DIN and DOUT are connectedtogether.Auto-CalibrationAuto-calibration can be enabled (ACAL bit in ADCONregister) to have the ADS1255/6 automatically initiate aself-calibration at the completion of a write command(WREG) that changes the data rate, PGA setting, or Bufferstatus.26ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004DATA READY (DRDY)The DRDY output is used as a status signal to indicatewhen conversion data is ready to be read. DRDY goes lowwhen new conversion data is available. It is reset highwhen all 24 bits have been read back using Read Data(RDATA) or Read Data Continuous (RDATAC) command.It also goes high when the new conversion data is beingupdated. Do not retrieve during this update period as thedata is invalid. If data is not retrieved, DRDY will only behigh during the update time as shown in Figure 24.STANDBY MODEThe standby mode shuts down all of the analog circuitryand most of the digital features. The oscillator continues torun to allow for fast wakeup. If enabled, clock outputD0/CLKOUT will also continue to run during duringStandby mode. To enter Standby mode, issue theSTANDBY command. To exit Standby mode, issue theWAKEUP command. DRDY will stay high after exitingStandby mode until valid data is ready. Standby mode canbe used to perform one-shot conversions; see SettlingTime Using One-Shot Mode section for more details.DataUpdatingPOWER-DOWN MODEHolding the SYNC/PDWN pin low for 20 DRDY cyclesactivates the Power-Down mode. During Power-Downmode, all circuitry is disabled including the oscillator andthe clock output.To exit Power-Down mode, take the SYNC/PDWN pinhigh. Upon exiting from Power-Down mode, theADS1255/6 crystal oscillator typically requires 30ms towake up. If using an external clock source, 8192 CLKINcycles are needed before conversions begin.DRDYFigure 24. DRDY with No Data RetreivalAfter changing the PGA, data rate, buffer status, writing tothe OFC or FSC registers, and enabling or disabling thesensor detect circuitry, perform a synchronizationoperation to force DRDY high. It will stay high until validdata is ready. If auto-calibration is enabled (by setting theACAL bit in the ADCON register), DRDY will go low afterthe self-calibration is complete and new data is valid.Exiting from Reset, Synchronization, Standby orPower-Down mode will also force DRDY high. DRDY willgo low as soon as valid data is ready.RESETThere are three methods to reset the ADS1255/6: theRESET input pin, RESET command, and a special SCLKreset pattern.When using the RESET pin, take it low to force a reset.Make sure to follow the minimum pulse width timingspecifications before taking the RESET pin back high.The RESET command takes effect after all eight bits havebeen shifted into DIN. Afterwards, the reset releasesautomatically.The ADS1255/6 can also be reset with a special pattern onSCLK (see Figure 2). Reset occurs on the falling edge ofthe last SCLK edge in the pattern. After performing theoperation, the reset releases automatically.On reset, the configuration registers are initialized to theirdefault state except for the ADCON register that controlsthe D0/CLKOUT pin. This register is only initialized to itsdefault state when RESET is performed using the RESETpin. After releasing from RESET, self-calibration isperformed, regardless of the reset method or the state ofthe ACAL bit before RESET.SYNCHRONIZATIONSynchronization of the ADS1255/6 is available tocoordinate the A/D conversion with an external event andalso to speed settling after an instantaneous change onthe analog inputs (see Conversion Time usingSynchronization section).Synchronization can be achieved either using theSYNC/PDWN pin or with the SYNC command. To use theSYNC/PDWN pin, take it low and then high, making sureto meet timing specification t16. Synchronization occurs onthe first rising edge of the master clock after SYNC/PDWNis taken high. No communication is possible on the serialinterface while SYNC/PDWN is low. If the SYNC/PDWNpin is held low for 20 DRDY periods the ADS1255/6 willenter Power-Down mode.To synchronize using the SYNC command, first shift in alleight bits of the SYNC command. This stops the operationof the ADS1255/6. When ready to synchronize, issue theWAKEUP command. Synchronization occurs on the firstrising edge of the master clock after the first SCLK used toshift in the WAKEUP command. After a synchronizationoperation, either with the SYNC/PDWN pin or the SYNCcommand, DRDY stays high until valid data is ready.POWER-UPAll of the configuration registers are initialized to theirdefault state at power-up. A self-calibration is thenperformed automatically. For the best performance, it isstrongly recommended to perform an additionalself-calibration by issuing the SELFCAL command afterthe power supplies and voltage reference have had timeto settle to their final values.27ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004APPLICATIONS INFORMATIONGENERAL RECOMMENDATIONSThe ADS1255 and ADS1256 are very high-resolution A/Dconverters. Getting the optimal performance from themrequires careful attention to their support circuitry andprinted circuit board (PCB) design. Figure 25 shows thebasic connections for the ADS1255. It is recommended touse a single ground plane for both the analog and digitalsupplies. This ground plane should be shared with thebypass capacitors and analog conditioning circuits.However, avoid using this ground plane for noisy digitalcomponents such as microprocessors. If a split groundplane is used with the ADS1255/6, make sure the analogand digital planes are tied together. There should not be avoltage difference between the ADS1255/6 analog anddigital ground pins (AGND and DGND).As with any precision circuit, use good supply bypassingtechniques. A smaller value ceramic capacitor in parallelwith a larger value tantalum or a larger value low-voltageceramic capacitor works well. Place the capacitors, inparticular the ceramic ones, close to the supply pins. Runthe digital logic off as low of voltage as possible. This helpsreduce coupling back to the analog inputs. Avoid ringingon the digital inputs. Small resistors (≈100Ω) in series withthe digital pins can help by controlling the traceimpedance. When not using the RESET or SYNC/PDWNinputs, tie directly to the ADS1255/6 DVDD pin.Pay special attention to the reference and analog inputs.These are the most critical circuits. On the voltagereference inputs, bypass with low equivalent seriesresistance (ESR) capacitors. Make these capacitors aslarge as possible to maximize the filtering on the reference.With the outstanding performance of the ADS1255/6, it iseasy for the voltage reference to limit overall performanceif not carefully selected. When using a stand-alonereference, make sure it is very low noise and very low drift.Ratiometric measurements, where the input signal andreference track each other, are somewhat less sensitive,but verify the reference signal is clean.Often times, only a simple RC filter (as shown in Figure 25)is needed on the inputs. This circuit limits thehigh-frequency noise near the modulator frequency; seethe Frequency Response section. Avoid low-gradedielectrics for the capacitors to minimize temperaturevariations and leakage. Keep the input traces as short aspossible and place the components close to the input pins.When using the ADS1256, make sure to filter all the inputchannels being used.+5V10µF0.1µF1249.9Ω47µF2.5V49.9Ω301ΩVINPVINN301Ω0.1µF0.1µF3100pF456100pF7+3.3V10µF0.1µF10AVDDAGNDVREFNVREFPAINCOMAIN0AIN1ADS1255D120D0/CLKOUT19SCLK18DIN17DOUT16DRDY15CS14XTAL1/CLKIN13XTAL212DGND117.68MHz18pF100Ω18pF100Ω100ΩSYNC/PDWNRESETDVDDFigure 25. ADS1255 Basic Connections28ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004DIGITAL INTERFACE CONNECTIONSThe ADS1255/6 5V tolerant SPI-, QSPI, andMICROWIRE-compatible interface easily connects to awide variety of microcontrollers. Figure 26 shows the basicconnection to TI’s MSP430 family of low-powermicrocontrollers. Figure 27 shows the connection tomicrocontrollers with an SPI interface like TI’s MSC12xxfamily or the 68HC11 family. Note that the MSC12xxincludes a high-resolution A/D converter; the ADS1255/6can be used to add additional channels of measurementor provide higher-speed conversions. Finally, Figure 28shows how to connect the ADS1255/6 to an 8xC51 UARTin serial mode 0 in a 2-wire configuration. Avoid using thecontinuous read mode (RDATAC) when DIN and DOUTare connected together.ADS1255ADS1256DINDOUTDRDYSCLKCS(1)(1)CSmaybetiedlow.MSC12xxor68HC11MOSIMISOINTSCKIOFigure 27. Connection to Microcontrollers withan SPI InterfaceADS1255ADS1256DINDOUTDRDYSCLKCS(1)(1)CSmaybetiedlow.P1.3P1.2P1.0P1.6P1.4MSP430ADS1255ADS1256DINDOUTDRDYSCLKCSDGNDP3.1xTXD8xC51P3.0/RXDFigure 26. Connection to MSP430MicrocontrollerFigure 28. Connection to 8xC51 MicrocontrollerUART with a 2-Wire Interface29ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004REGISTER MAPThe operation of the ADS1255/6 is controlled through a set of registers. Collectively, the registers contain all the informationneeded to configure the part, such as data rate, multiplexer settings, PGA setting, calibration, etc., and are listed inTable 23.Table 23. Register MapADDRESS00h01h02h03h04h05h06h07h08h09h0AhREGISTERSTATUSMUXADCONDRATEIOOFC0OFC1OFC2FSC0FSC1FSC2RESETVALUEx1H01H20HF0HE0HxxHxxHxxHxxHxxHxxHBIT 7ID3PSEL30DR7DIR3OFC07OFC15OFC23FSC07FSC15FSC23BIT 6ID2PSEL2CLK1DR6DIR2OFC06OFC14OFC22FSC06FSC14FSC22BIT 5ID1PSEL1CLK0DR5DIR1OFC05OFC13OFC21FSC05FSC13FSC21BIT 4ID0PSEL0SDCS1DR4DIR0OFC04OFC12OFC20FSC04FSC12FSC20BIT 3ORDERNSEL3SDCS0DR3DIO3OFC03OFC11OFC19FSC03FSC11FSC19BIT 2ACALNSEL2PGA2DR2DIO2OFC02OFC10OFC18FSC02FSC10FSC18BIT 1BUFENNSEL1PGA1DR1DIO1OFC01OFC09OFC17FSC01FSC09FSC17BIT 0DRDYNSEL0PGA0DR0DIO0OFC00OFC08OFC16FSC00FSC08FSC16STATUS : STATUS REGISTER (ADDRESS 00h)Reset Value = x1hBIT 7IDBIT 6IDBIT 5IDBIT 4IDBIT 3ORDERBIT 2ACALBIT 1BUFENBIT 0DRDYBits 7-4ID3, ID2, ID1, ID0 Factory Programmed Identification Bits (Read Only)Bit 3ORDER: Data Output Bit Order0 = Most Significant Bit First (default)1 = Least Significant Bit FirstInput data is always shifted in most significant byte and bit first. Output data is always shifted out most significantbyte first. The ORDER bit only controls the bit order of the output data within the byte.ACAL: Auto-Calibration0 = Auto-Calibration Disabled (default)1 = Auto-Calibration EnabledWhen Auto-Calibration is enabled, self-calibration begins at the completion of the WREG command that changesthe PGA (bits 0-2 of ADCON register), DR (bits 7-0 in the DRATE register) or BUFEN (bit 1 in the STATUS register)values.BUFEN: Analog Input Buffer Enable0 = Buffer Disabled (default)1 = Buffer EnabledDRDY: Data Ready (Read Only)This bit duplicates the state of the DRDY pin.Bit 2Bit 1Bit 030ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004MUX : Input Multiplexer Control Register (Address 01h)Reset Value = 01hBIT 7PSEL3BIT 6PSEL2BIT 5PSEL1BIT 4PSEL0BIT 3NSEL3BIT 2NSEL2BIT 1NSEL1BIT 0NSEL0Bits 7-4PSEL3, PSEL2, PSEL1, PSEL0: Positive Input Channel (AINP) Select0000 = AIN0 (default)0001 = AIN10010 = AIN2 (ADS1256 only)0011 = AIN3 (ADS1256 only)0100 = AIN4 (ADS1256 only)0101 = AIN5 (ADS1256 only)0110 = AIN6 (ADS1256 only)0111 = AIN7 (ADS1256 only)1xxx = AINCOM (when PSEL3 = 1, PSEL2, PSEL1, PSEL0 are “don’t care”)NOTE:When using an ADS1255 make sure to only select the available inputs.Bits 3-0NSEL3, NSEL2, NSEL1, NSEL0: Negative Input Channel (AINN)Select0000 = AIN00001 = AIN1 (default)0010 = AIN2 (ADS1256 only)0011 = AIN3 (ADS1256 only)0100 = AIN4 (ADS1256 only)0101 = AIN5 (ADS1256 only)0110 = AIN6 (ADS1256 only)0111 = AIN7 (ADS1256 only)1xxx = AINCOM (when NSEL3 = 1, NSEL2, NSEL1, NSEL0 are “don’t care”)NOTE:When using an ADS1255 make sure to only select the available inputs.ADCON: A/D Control Register (Address 02h)Reset Value = 20hBIT 70BIT 6CLK1BIT 5CLK0BIT 4SDCS1BIT 3SDCS0BIT 2PGA2BIT 1PGA1BIT 0PGA0Bit 7Reserved, always 0 (Read Only)Bits 6-5CLK1, CLK0: D0/CLKOUT Clock Out Rate Setting00 = Clock Out OFF01 = Clock Out Frequency = fCLKIN (default)10 = Clock Out Frequency = fCLKIN/211 = Clock Out Frequency = fCLKIN/4When not using CLKOUT, it is recommended that it be turned off.Bits 4-2SDCS1, SCDS0: Sensor Detect Current Sources00 = Sensor Detect OFF (default)01 = Sensor Detect Current = 0.5µA10 = Sensor Detect Current = 2µA11 = Sensor Detect Current = 10µAThe Sensor Detect Current Sources can be activated to verify the integrity of an external sensor supplying a signal to theADS1255/6. A shorted sensor produces a very small signal while an open-circuit sensor produces a very large signal.Bits 2-0PGA2, PGA1, PGA0: Programmable Gain Amplifier Setting000 = 1 (default)001 = 2010 = 4011 = 8100 = 16101 = 32110 = 111 = 31ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004DRATE: A/D Data Rate (Address 03h)Reset Value = F0hBIT 7DR7BIT 6DR6BIT 5DR5BIT 4DR4BIT 3DR3BIT 2DR2BIT 1DR1BIT 0DR0The 16 valid Data Rate settings are shown below. Make sure to select a valid setting as the invalid settings may produceunpredictable results.Bits 7-0DR[7: 0]: Data Rate Setting(1)11110000 = 30,000SPS (default)11100000 = 15,000SPS11010000 = 7,500SPS11000000 = 3,750SPS10110000 = 2,000SPS10100001 = 1,000SPS10010010 = 500SPS10000010 = 100SPS01110010 = 60SPS01100011 = 50SPS01010011 = 30SPS01000011 = 25SPS00110011 = 15SPS00100011 = 10SPS00010011 = 5SPS00000011 = 2.5SPS(1)for fCLKIN = 7.68MHz. Data rates scale linearly with fCLKIN.I/O: GPIO Control Register (Address 04H)Reset Value = E0hBIT 7DIR3BIT 6DIR2BIT 5DIR1BIT 4DIR0BIT 3DIO3BIT 2DIO2BIT 1DIO1BIT 0DIO0The states of these bits control the operation of the general−purpose digital I/O pins. The ADS1256 has 4 I/O pins: D3, D2,D1, and D0/CLKOUT. The ADS1255 has two digital I/O pins: D1 and D0/CLKOUT. When using an ADS1255, the registerbits DIR3, DIR2, DIO3, and DIO2 can be read from and written to but have no effect.Bit 7DIR3, Digital I/O Direction for Digital I/O Pin D3 (used on ADS1256 only)0 = D3 is an output1 = D3 is an input (default)DIR2, Digital I/O Direction for Digital I/O Pin D2 (used on ADS1256 only)0 = D2 is an output1 = D2 is an input (default)DIR1, Digital I/O Direction for Digital I/O Pin D10 = D1 is an output1 = D1 is an input (default)DIR0, Digital I/O Direction for Digital I/O Pin D0/CLKOUT0 = D0/CLKOUT is an output (default)1 = D0/CLKOUT is an inputBit 6Bit 5Bit 4Bits 3-0DI0[3:0]: Status of Digital I/O Pins D3, D2, D1, D0/CLKOUTReading these bits will show the state of the corresponding digital I/O pin, whether if the pin is configured as aninput or output by DIR3-DIR0. When the digital I/O pin is configured as an output by the DIR bit, writing to thecorresponding DIO bit will set the output state. When the digital I/O pin is configured as an input by the DIR bit,writing to the corresponding DIO bit will have no effect. When DO/CLKOUT is configured as an output andCLKOUT is enabled (using CLK1, CLK0 bits in the ADCON register), writing to DIO0 will have no effect.32ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004OFC0: Offset Calibration Byte 0, least significant byte (Address 05h)Reset value depends on calibration results.BIT 7OFC07BIT 6OFC06BIT 5OFC05BIT 4OFC04BIT 3OFC03BIT 2OFC02BIT 1OFC01BIT 0OFC00OFC1: Offset Calibration Byte 1 (Address 06h)Reset value depends on calibration results.BIT 7OFC15BIT 6OFC14BIT 5OFC13BIT 4OFC12BIT 3OFC11BIT 2OFC10BIT 1OFC09BIT 0OFC08OFC: Offset Calibration Byte 2, most significant byte (Address 07h)Reset value depends on calibration results.BIT 7OFC23BIT 6OFC22BIT 5OFC21BIT 4OFC20BIT 3OFC19BIT 2OFC18BIT 1OFC17BIT 0OFC16FSC0: Full−scale Calibration Byte 0, least significant byte (Address 08h)Reset value depends on calibration results.BIT 7FSC07BIT 6FSC06BIT 5FSC05BIT 4FSC04BIT 3FSC03BIT 2FSC02BIT 1FSC01BIT 0FSC00FSC1: Full−scale Calibration Byte 1 (Address 09h)Reset value depends on calibration results.BIT 7FSC15BIT 6FSC14BIT 5FSC13BIT 4FSC12BIT 3FSC11BIT 2FSC10BIT 1FSC09BIT 0FSC08FSC2: Full−scale Calibration Byte 2, most significant byte (Address 0Ah)Reset value depends on calibration results.BIT 7FSC23BIT 6FSC22BIT 5FSC21BIT 4FSC20BIT 3FSC19BIT 2FSC18BIT 1FSC17BIT 0FSC1633ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004COMMAND DEFINITIONSThe commands summarized in Table 24 control the operation of the ADS1255/6. All of the commands are stand-aloneexcept for the register reads and writes (RREG, WREG) which require a second command byte plus data. Additionalcommand and data bytes may be shifted in without delay after the first command byte. The ORDER bit in the STATUSregister sets the order of the bits within the output data. CS must stay low during the entire command sequence.Table 24. Command DefinitionsCOMMANDWAKEUPRDATARDATACSDATACRREGWREGSELFCALSELFOCALSELFGCALSYSOCALSYSGCALSYNCSTANDBYRESETWAKEUPDESCRIPTIONCompletes SYNC and Exits Standby ModeRead DataRead Data ContinuouslyStop Read Data ContinuouslyRead from REG rrrWrite to REG rrrOffset and Gain Self-CalibrationOffset Self-CalibrationGain Self-CalibrationSystem Offset CalibrationSystem Gain CalibrationSynchronize the A/D ConversionBegin Standby ModeReset to Power-Up ValuesCompletes SYNC and Exits Standby Mode1ST COMMAND BYTE0000 00000000 00010000 00110000 11110001 rrrr0101 rrrr1111 00001111 00011111 00101111 00111111 01001111 11001111 11011111 11101111 1111(00h)(01h)(03h)(0Fh)(1xh)(5xh)(F0h)(F1h)(F2h)(F3h)(F4h)(FCh)(FDh)(FEh)(FFh)0000 nnnn0000 nnnn2ND COMMAND BYTENOTE:n = number of registers to be read/written − 1. For example, to read/write three registers, set nnnn = 2 (0010).r = starting register address for read/write commands.RDATA: Read DataDescription: Issue this command after DRDY goes low to read a single conversion result. After all 24 bits have been shiftedout on DOUT, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until newdata is being updated. See the Timing Characteristics for the required delay between the end of the RDATA command andthe beginning of shifting data on DOUT: t6.DRDYDIN00000001DOUTt6SCLK•••MSBMid−ByteLSB•••Figure 29. RDATA Command Sequence34ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004RDATAC: Read Data ContinuousDescription: Issue command after DRDY goes low to enter the Read Data Continuous mode. This mode enables thecontinuous output of new data on each DRDY without the need to issue subsequent read commands. After all 24 bits havebeen read, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new datais being updated. This mode may be terminated by the Stop Read Data Continuous command (STOPC). Because DINis constantly being monitored during the Read Data Continuous mode for the STOPC or RESET command, do not usethis mode if DIN and DOUT are connected together. See the Timing Characteristics for the required delay between the endof the RDATAC command and the beginning of shifting data on DOUT: t6.DRDYDIN00000011t6DOUT24Bits24BitsFigure 30. RDATAC Command SequenceOn the following DRDY, shift out data by applying SCLKs. The Read Data Continuous mode terminates if input_data equalsthe STOPC or RESET command in any of the three bytes on DIN.DRDYDINinput_datainput_datainput_dataDOUTMSBMid−ByteLSBFigure 31. DIN and DOUT Command Sequence During Read Continuous ModeSTOPC: Stop Read Data ContinuousDescription: Ends the continuous data output mode. (see RDATAC). The command must be issued after DRDY goes lowand completed before DRDY goes high.DRDYDIN0001111Figure 32. STOPC Command Sequence35ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004RREG: Read from RegistersDescription: Output the data from up to 11 registers starting with the register address specified as part of the command.The number of registers read will be one plus the second byte of the command. If the count exceeds the remaining registers,the addresses will wrap back to the beginning.1st Command Byte: 0001 rrrr where rrrr is the address of the first register to read.2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to read – 1. See the Timing Characteristics for therequired delay between the end of the RREG command and the beginning of shifting data on DOUT: t6.DIN0001000100000001t6MUXDataByteADCONDataByte1stCommand2ndCommandByteByteDOUTFigure 33. RREG Command Example: Read Two Registers Starting from Register 01h (multiplexer)WREG: Write to RegisterDescription: Write to the registers starting with the register specified as part of the command. The number of registers thatwill be written is one plus the value of the second byte in the command.1st Command Byte: 0101 rrrr where rrrr is the address to the first register to be written.2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to be written – 1.Data Byte(s): data to be written to the registers.DIN010100111stCommandByte000000012ndCommandByteDRATEDataIODataDataByteDataByteFigure 34. WREG Command Example: Write Two Registers Starting from 03h (DRATE)SELFCAL: Self Offset and Gain CalibrationDescription: Performs a self offset and self gain calibration. The Offset Calibration Register (OFC) and Full-ScaleCalibration Register (FSC) are updated after this operation. DRDY goes high at the beginning of the calibration. It goeslow after the calibration completes and settled data is ready. Do not send additional commands after issuing this commanduntil DRDY goes low indicating that the calibration is complete.SELFOCAL: Self Offset CalibrationDescription: Performs a self offset calibration. The Offset Calibration Register (OFC) is updated after this operation. DRDYgoes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do notsend additional commands after issuing this command until DRDY goes low indicating that the calibration is complete.SELFGCAL: Self Gain CalibrationDescription: Performs a self gain calibration. The Full-Scale Calibration Register (FSC) is updated with new values afterthis operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settleddata is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that thecalibration is complete.36ADS1255ADS1256www.ti.comSBAS288C − JUNE 2003 − REVISED MARCH 2004SYSOCAL: System Offset CalibrationDescription: Performs a system offset calibration. The Offset Calibration Register (OFC) is updated after this operation.DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready.Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration iscomplete.SYSGCAL: System Gain CalibrationDescription: Performs a system gain calibration. The Full-Scale Calibration Register (FSC) is updated after this operation.DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready.Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration iscomplete.SYNC: Synchronize the A/D ConversionDescription: This command synchronizes the A/D conversion. To use, first shift in the command. Then shift in theWAKEUP command. Synchronization occurs on the first CLKIN rising edge after the first SCLK used to shift in theWAKEUP command.DIN11111100(SYNC)••••••00000000(WAKEUP)••••••SCLKCLKINSynchronizationOccursHereFigure 35. SYNC Command SequenceSTANDBY: Standby Mode / One-Shot ModeDescription: This command puts the ADS1255/6 into a low-power Standby mode. After issuing the STANDBY command,make sure there is no more activity on SCLK while CS is low, as this will interrupt Standby mode. If CS is high, SCLK activityis allowed during Standby mode. To exit Standby mode, issue the WAKEUP command. This command can also be usedto perform single conversions (see One-Shot Mode section) .DIN11111101(SYNC)00000000(WAKEUP)SCLKNormalModeStandbyModeNormalModeFigure 36. STANDBY Command SequenceWAKEUP: Complete Synchronization or Exit Standby ModeDescription: Used in conjunction with the SYNC and STANDBY commands. Two values (all zeros or all ones) areavailable for this command.RESET: Reset Registers to Default ValuesDescription: Returns all registers except CLKON to their default values. This command will also stop the Read Continuousmode: in this case, issue the RESET command after DRDY goes low.37MECHANICAL DATAMSSO002E – JANUARY 1995 – REVISED DECEMBER 2001DB (R-PDSO-G**) 28 PINS SHOWN0,65280,380,22150,15MPLASTIC SMALL-OUTLINE0,250,095,605,008,207,40Gage Plane1A140°–ā8°0,250,950,55Seating Plane2,00 MAX0,05 MIN0,10PINS **DIMA MAX146,50166,50207,50248,502810,503010,503812,90A MIN5,905,906,907,909,909,9012,304040065/E 12/01NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-150POST OFFICE BOX 655303 DALLAS, TEXAS 75265•IMPORTANT NOTICE
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