专利内容由知识产权出版社提供
专利名称：SEMICONDUCTOR LAYOUT GENERATION发明人：Atsushi Azuma,Yuping Cui,James A.
Culp,Marco Facchini,Shaoning Yao
申请号：US15173756申请日：20160606
公开号：US20170351799A1公开日：20171207
专利附图：
摘要：Semiconductor layout generation includes: calculating, for a design ruleconstraint, a slack value for a subset of elements of a proposed semiconductor layout;generating a plurality of alternative layouts, where each of the alternative layouts
includes a variation of interdependent characteristics of the subset of elements and aslack value for the subset of elements of each of the alternative layouts is less than thecalculated slack value of subset of elements of the proposed layout; and calculating, bythe layout design module for each of the alternative layouts, a risk value indicating thealternative layout's risk of fabrication failure.
申请人：GLOBALFOUNDRIES Inc.
地址：Grand Cayman KY
国籍：KY
更多信息请下载全文后查看
