SI7450DP-T1-GE3;中文规格书,Datasheet资料

Vishay Siliconix

N-Channel 200-V (D-S) MOSFET

PRODUCT SUMMARY

VDS (V)200

RDS(on) (Ω)0.080 at VGS = 10 V 0.090 at VGS = 6 V

ID (A)5.35.0

FEATURES

•Halogen-free According to IEC 61249-2-21

Available

•TrenchFET® Power MOSFETs

•New Low Thermal Resistance PowerPAK®

Package with Low 1.07 mm Profile •PWM Optimized for Fast Switching

•100 % Rg Tested

PowerPAK SO-8APPLICATIONS

5.15 mm6.15 mmS123SS •Primary Side Switch for High Density DC/DC •Telecom/Server 48 V DC/DC •Industrial and 42 V Automotive

DG4D8765DDDGN-Channel MOSFETBottom ViewOrdering Information: Si7450DP-T1-E3 (Lead (Pb)-free) Si7450DP-T1-GE3 (Lead (Pb)-free and Halogen-free)SABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter

Drain-Source Voltage Gate-Source Voltage

Continuous Drain Current (TJ = 150°C)aPulsed Drain Current Avalanche Current

Continuous Source Current (Diode Conduction)aMaximum Power Dissipationa

Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)b, c

TA = 25 °CTA = 70 °CTA = 25 °CTA = 70 °C

Symbol VDSVGS

IDIDMIASISPDTJ, Tstg

10 s

Steady State 200± 20

5.34.3

4015

4.35.23.3

- 55 to 150

260

1.61.91.23.22.6

AUnit V

W°C

THERMAL RESISTANCE RATINGS

Parameter Symbol TypicalMaximumUnit t ≤ 10 s1924RthJAMaximum Junction-to-Ambienta

Steady State5265°C/W

RthJC1.51.8Maximum Junction-to-Case (Drain)Steady StateNotes:

a.Surface Mounted on 1\" x 1\" FR4 board.

b.See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is notrequired to ensure adequate bottom side solder interconnection.

c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.

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Si7450DP

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SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Condition Min.Typ.Static

Gate Threshold VoltageGate-Body Leakage

Zero Gate Voltage Drain CurrentOn-State Drain Currenta

Drain-Source On-State ResistanceaForward TransconductanceaDiode Forward VoltageaDynamicb

Total Gate ChargeGate-Source ChargeGate-Drain ChargeGate ResistanceTurn-On Delay TimeRise Time

Turn-Off Delay TimeFall Time

Source-Drain Reverse Recovery Time

Qg Qgs Qgd Rgtd(on) trtd(off) tftrr

IF = 2.8 A, dI/dt = 100 A/µsVDD = 100 V, RL = 25 Ω ID ≅ 4.0 A, VGEN = 10 V, Rg = 6 Ω

0.2

VDS = 100 V, VGS = 10 V, ID = 4.0 A

347.512.00.851420322570

1.520305035100

nsΩ

42

nC

VGS(th) IGSSIDSSID(on) RDS(on) gfs VSD

VDS = VGS, ID = 250 µA VDS = 0 V, VGS = ± 20 V VDS = 200 V, VGS = 0 V VDS = 200 V, VGS = 0 V, TJ = 55 °C

VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 4.0 A VGS = 6.0 V, ID = 4.0 A VDS = 15 V, ID = 5 A IS = 2.8 A, VGS = 0 V

40

0.0650.070190.75

1.20.0800.090

2.0

4.515

V

±100 nA

µAAΩSV

Max.

Unit Notes:

a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.

b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS 25°C, unless otherwise noted40VGS = 10 V thru 6 V3230ID- Drain Current (A)ID- Drain Current (A)24252015105002468VDS - Drain-to-Source Voltage (V)4 V01001234VGS - Gate-to-Source Voltage (V)TC = 125 °C25 °C- 55 °C50351685 VOutput CharacteristicsTransfer Characteristicswww.vishay.com2Document Number: 71432S09-0227-Rev. E, 09-Feb-09

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Si7450DP

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TYPICAL CHARACTERISTICS 25°C, unless otherwise noted

0.202500RDS(on)- On-Resistance (Ω)0.15C - Capacitance (pF)2000Ciss15000.10VGS = 6 V1000VGS = 10 V0.05500CrssCoss0.000816243240004080120160200ID - Drain Current (A)VDS - Drain-to-Source Voltage (V)On-Resistance vs. Drain Current20VGS- Gate-to-Source Voltage (V)VDS = 100 VID = 4.0 ARDS(on)- On-Resistance (Normalized)162.5VGS = 10 VID = 4.0 A2.0Capacitance121.581.040.50015304560Qg - Total Gate Charge (nC)0.0-50-250255075100125150TJ - Junction Temperature (°C)Gate Charge0.25On-Resistance vs. Junction Temperature50RDS(on)- On-Resistance (Ω)0.20ID = 4.0 A0.15IS- Source Current (A)TJ = 150 °C100.10TJ = 25 °C0.0510.00.000.20.40.60.81.01.20246810VSD - Source-to-Drain Voltage (V)VGS - Gate-to-Source Voltage (V)Source-Drain Diode Forward VoltageOn-Resistance vs. Gate-to-Source Voltage

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TYPICAL CHARACTERISTICS 25°C, unless otherwise noted1.01000.5VGS(th)Variance (V)ID = 250 µAPower (W)0.08060-0.540-1.020-1.5-50-250255075100TJ - Temperature (°C)12515000.0010.010.1Time (s)110Threshold Voltage21Normalized Effective TransientThermal ImpedanceDuty Cycle = 0.5Single Pulse Power, Junction-to-Ambient0.20.10.10.05t1Notes:PDM0.02Single Pulse0.0110-410-310-210-11Square Wave Pulse Duration (s)t21. Duty Cycle, D =2. Per Unit Base = RthJA = 68°C/W3. TJM - TA = PDMZthJA(t)4. Surface Mountedt1t210100600Normalized Thermal Transient Impedance, Junction-to-Ambient21Normalized Effective TransientThermal ImpedanceDuty Cycle = 0.50.20.10.10.050.02Single Pulse0.0110-410-310-210-1Square Wave Pulse Duration (s)110Normalized Thermal Transient Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see www.vishay.com/ppg?71432.www.vishay.com4Document Number: 71432S09-0227-Rev. E, 09-Feb-09

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Package Information

Vishay Siliconix

PowerPAK® SO-8, (SINGLE/DUAL)

HWθM122D1D34L1E3θθE2E4KLD412D2D534bbL1D12K1D534DθA10.150 ± 0.008D2ZecDetail ZD3(2x)D42E1EABackside View of Single PadHKE2E4D2Notes1.Inch will govern.2Dimensions exclusive of mold gate burrs.3.Dimensions exclusive of mold flash and cutting burrs.E3Backside View of Dual PadMILLIMETERS

DIM.AA1bcDD1D2D3D4D5EE1E2E3 E4eKK1HLL1θWM

ECN: T10-0055-Rev. J, 15-Feb-10DWG: 5881

0.560.510.510.060°0.156.055.793.483.68MIN.0.970.000.330.235.054.803.561.32

NOM.1.04-0.410.285.154.903.761.500.57 TYP.3.98 TYP.6.155.3.663.780.75 TYP.1.27 BSC1.27 TYP.

-0.610.610.13-0.250.125 TYP.

-0.710.710.2012°0.36

0.0220.0200.0200.0020°0.006

6.255.993.843.91

0.2380.2280.1370.145

MAX.1.120.050.510.335.265.003.911.68

MIN.0.0380.0000.0130.0090.1990.10.1400.052

INCHESNOM.0.041-0.0160.0110.2030.1930.1480.0590.0225 TYP.0.157 TYP.0.2420.2320.1440.1490.030 TYP.0.050 BSC0.050 TYP.

-0.0240.0240.005-0.0100.005 TYP.

-0.0280.0280.00812°0.0140.2460.2360.1510.154MAX.0.0440.0020.0200.0130.2070.1970.1540.066

Document Number: 71655Revison: 15-Feb-10

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AN821

Vishay Siliconix

PowerPAK® SO-8 Mounting and Thermal Considerations

Wharton McDaniel

MOSFETs for switching applications are now availablewith die on resistances around 1 mΩ and with thecapability to handle 85 A. While these die capabilitiesrepresent a major advance over what was availablejust a few years ago, it is important for power MOSFETpackaging technology to keep pace. It should be obvi-ous that degradation of a high performance die by thepackage is undesirable. PowerPAK is a new packagetechnology that addresses these issues. In this appli-cation note, PowerPAK’s construction is described.Following this mounting information is presentedincluding land patterns and soldering profiles for max-imum reliability. Finally, thermal and electrical perfor-mance is discussed.

THE PowerPAK PACKAGE

The PowerPAK package was developed around theSO-8 package (Figure 1). The PowerPAK SO-8 uti-lizes the same footprint and the same pin-outs as thestandard SO-8. This allows PowerPAK to be substi-tuted directly for a standard SO-8 package. Being aleadless package, PowerPAK SO-8 utilizes the entireSO-8 footprint, freeing space normally occupied by theleads, and thus allowing it to hold a larger die than astandard SO-8. In fact, this larger die is slightly largerthan a full sized DPAK die. The bottom of the die attachpad is exposed for the purpose of providing a direct,low resistance thermal path to the substrate the deviceis mounted on. Finally, the package height is lowerthan the standard SO-8, making it an excellent choicefor applications with space constraints.

PowerPAK SO-8 SINGLE MOUNTING

The PowerPAK single is simple to use. The pinarrangement (drain, source, gate pins) and the pindimensions are the same as standard SO-8 devices(see Figure 2). Therefore, the PowerPAK connectionpads match directly to those of the SO-8. The only dif-ference is the extended drain connection area. To takeimmediate advantage of the PowerPAK SO-8 singledevices, they can be mounted to existing SO-8 landpatterns.

Standard SO-8PowerPAK SO-8

Figure 2.

The minimum land pattern recommended to take fulladvantage of the PowerPAK thermal performance seeApplication Note 826, Recommended Minimum PadPatterns With Outline Drawing Access for Vishay Sili-conix MOSFETs. Click on the PowerPAK SO-8 singlein the index of this document.

In this figure, the drain land pattern is given to make fullcontact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, andtop of the drawn pattern. This extension will serve toincrease the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to thePC board and therefore to the ambient. Note thatincreasing the drain land area beyond a certain pointwill yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditionsof board configuration, copper weight and layer stack,experiments have found that more than about 0.25 to0.5 in2 of additional copper (in addition to the drainland) will yield little improvement in thermal perfor-mance.

Figure 1. PowerPAK 1212 Devices

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PowerPAK SO-8 DUAL

The pin arrangement (drain, source, gate pins) and thepin dimensions of the PowerPAK SO-8 dual are thesame as standard SO-8 dual devices. Therefore, thePowerPAK device connection pads match directly tothose of the SO-8. As in the single-channel package,the only exception is the extended drain connectionarea. Manufacturers can likewise take immediateadvantage of the PowerPAK SO-8 dual devices bymounting them to existing SO-8 dual land patterns.To take the advantage of the dual PowerPAK SO-8’sthermal performance, the minimum recommendedland pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With OutlineDrawing Access for Vishay Siliconix MOSFETs. Clickon the PowerPAK 1212-8 dual in the index of this doc-ument.

The gap between the two drain pads is 24 mils. Thismatches the spacing of the two drain pads on the Pow-erPAK SO-8 dual package.

Ramp-Up Rate

Temperature at 155 ± 15 °C Temperature Above 180 °C Maximum Temperature Ramp-Down RateFor the lead (Pb)-free solder profile, see http://www.vishay.com/doc?73257.

+ 6 °C /Second Maximum 120 Seconds Maximum 70 - 180 Seconds 240 + 5/- 0 °C

+ 6 °C/Second Maximum

Time at Maximum Temperature 20 - 40 Seconds

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solderreflow reliability requirements. Devices are subjectedto solder reflow as a test preconditioning and are thenreliability-tested using temperature cycle, bias humid-ity, HAST, or pressure pot. The solder reflow tempera-ture profile used, and the temperatures and timeduration, are shown in Figures 3 and 4.

Figure 3. Solder Reflow Temperature Profile

10 s (max)210 - 220 °C3 °C(max)183 °C140 - 170 °C50 s (max)3 °C(max)60 s (min)Pre-Heating ZoneReflow Zone4 ° C/s (max)Maximum peak temperature at 240 °C is allowed.Figure 3. Solder Reflow Temperatures and Time Durations

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THERMAL PERFORMANCEIntroduction

A basic measure of a device’s thermal performance isthe junction-to-case thermal resistance, Rθjc, or thejunction-to-foot thermal resistance, Rθjf. This parameteris measured for the device mounted to an infinite heatsink and is therefore a characterization of the deviceonly, in other words, independent of the properties of theobject to which the device is mounted. Table 1 shows acomparison of the DPAK, PowerPAK SO-8, and stan-dard SO-8. The PowerPAK has thermal performanceequivalent to the DPAK, while having an order of magni-tude better thermal performance over the SO-8. TABLE 1.

DPAK and PowerPAK SO-8

Equivalent Steady State Performance

DPAK

Thermal Resistance Rθjc

PowerPAK

SO-81.0 °C/W

StandardSO-816 °C/W

Because of the presence of the trough, this result sug-gests a minimum performance improvement of 10 °C/Wby using a PowerPAK SO-8 in a standard SO-8 PCboard mount.

The only concern when mounting a PowerPAK on astandard SO-8 pad pattern is that there should be notraces running between the body of the MOSFET.Where the standard SO-8 body is spaced away from thepc board, allowing traces to run underneath, the Power-PAK sits directly on the pc board.

Thermal Performance - Spreading Copper

Designers may add additional copper, spreading cop-per, to the drain pad to aid in conducting heat from adevice. It is helpful to have some information about thethermal performance for a given area of spreading cop-per.

Figure 6 shows the thermal resistance of a PowerPAKSO-8 device mounted on a 2-in. 2-in., four-layer FR-4PC board. The two internal layers and the backside layerare solid copper. The internal layers were chosen assolid copper to model the large power and groundplanes common in many applications. The top layer wascut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken.The results indicate that an area above 0.3 to 0.4 squareinches of spreading copper gives no additional thermalperformance improvement. A subsequent experimentwas run where the copper on the back-side wasreduced, first to 50 % in stripes to mimic circuit traces,and then totally removed. No significant effect wasobserved.

Rth vs. Spreading Copper(0 %, 50 %, 100 % Back Copper)561.2 °C/W

Thermal Performance on Standard SO-8 Pad PatternBecause of the common footprint, a PowerPAK SO-8can be mounted on an existing standard SO-8 pad pat-tern. The question then arises as to the thermal perfor-mance of the PowerPAK device under these conditions.A characterization was made comparing a standard SO-8and a PowerPAK device on a board with a trough cut outunderneath the PowerPAK drain pad. This configurationrestricted the heat flow to the SO-8 land pads. Theresults are shown in Figure 5.

Si4874DY vs. Si7446DP PPAK on a 4-Layer BoardSO-8 Pattern, Trough Under Drain6050Impedance (C/watts)40Si4874DY30Si7446DP2010Impedance (C/watts)5141100 %0 %00.00010.011Pulse Duration (sec)1001000050 %360.000.250.500.751.001.251.501.752.00Figure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal PathFigure 6. Spreading Copper Junction-to-Ambient Performance

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SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8

In any design, one must take into account the change inMOSFET rDS(on) with temperature (Figure 7).

On-Resistance vs. Junction Temperature1.8VGS = 10 VID = 23 ArDS(on)- On-Resistance ()(Normalized)1.6Suppose each device is dissipating 2.7 W. Using thejunction-to-foot thermal resistance characteristics of thePowerPAK SO-8 and the standard SO-8, the die tem-perature is determined to be 107 °C for the PowerPAK(and for DPAK) and 148 °C for the standard SO-8. Thisis a 2 °C rise above the board temperature for the Pow-erPAK and a 43 °C rise for the standard SO-8. Referringto Figure 7, a 2 °C difference has minimal effect onrDS(on) whereas a 43C difference has a significant effecton rDS(on).

Minimizing the thermal rise above the board tempera-ture by using PowerPAK has not only eased the thermaldesign but it has allowed the device to run cooler, keeprDS(on) low, and permits the device to handle more cur-rent than the same MOSFET die in the standard SO-8package.

1.41.21.00.80.6-50-250255075100125150TJ- Junction Temperature (°C)Figure 7. MOSFET rDS(on) vs. TemperatureA MOSFET generates internal heat due to the currentpassing through the channel. This self-heating raisesthe junction temperature of the device above that of thePC board to which it is mounted, causing increasedpower dissipation in the device. A major source of thisproblem lies in the large values of the junction-to-footthermal resistance of the SO-8 package.

PowerPAK SO-8 minimizes the junction-to-board ther-mal resistance to where the MOSFET die temperature isvery close to the temperature of the PC board. Considertwo devices mounted on a PC board heated to 105 °Cby other components on the board (Figure 8).

CONCLUSIONS

PowerPAK SO-8 has been shown to have the samethermal performance as the DPAK package while hav-ing the same footprint as the standard SO-8 package.The PowerPAK SO-8 can hold larger die approximatelyequal in size to the maximum that the DPAK can accom-modate implying no sacrifice in performance because ofpackage limitations.

Recommended PowerPAK SO-8 land patterns are pro-vided to aid in PC board layout for designs using thisnew package.

Thermal considerations have indicated that significantadvantages can be gained by using PowerPAK SO-8devices in designs where the PC board was laid out forthe standard SO-8. Applications experimental data gavethermal performance data showing minimum and typicalthermal performance in a SO-8 environment, plus infor-mation on the optimum thermal performance obtainableincluding spreading copper. This further emphasized theDPAK equivalency.

PowerPAK SO-8 therefore has the desired small sizecharacteristics of the SO-8 combined with the attractivethermal characteristics of the DPAK package.

PowerPAK SO-8107 °CStandard SO-8148 °C0.8 °C/WPC Board at 105 °C16C/WFigure 8. Temperature of Devices on a PC Boardwww.vishay.com4Document Number 71622

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Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single

0.260(6.61)0.150(3.81)0.024(0.61)(3.91)0.026(0.66)(1.27)0.0500.050(1.27)0.032(0.82)0.040(1.02)Recommended Minimum PadsDimensions in Inches/(mm)Return to IndexReturn to Index(4.42)0.1540.174APPLICATION NOTE

Document Number: 72599Revision: 21-Jan-08

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SI7450DP-T1-GE3