DS90CR287_04资料

DS90CR287/DS90CR288A+3.3VRisingEdgeDataStrobeLVDS28-BitChannelLink-85MHzJuly2004

DS90CR287/DS90CR288A

+3.3VRisingEdgeDataStrobeLVDS28-BitChannelLink-85MHz

GeneralDescription

TheDS90CR287transmitterconverts28bitsofLVCMOS/LVTTLdataintofourLVDS(LowVoltageDifferentialSignal-ing)datastreams.Aphase-lockedtransmitclockistransmit-tedinparallelwiththedatastreamsoverafifthLVDSlink.Everycycleofthetransmitclock28bitsofinputdataaresampledandtransmitted.TheDS90CR288Areceivercon-vertsthefourLVDSdatastreamsbackinto28bitsofLVCMOS/LVTTLdata.Atatransmitclockfrequencyof85MHz,28bitsofTTLdataaretransmittedatarateof595MbpsperLVDSdatachannel.Usinga85MHzclock,thedatathroughputis2.38Gbit/s(297.5Mbytes/sec).

ThischipsetisanidealmeanstosolveEMIandcablesizeproblemsassociatedwithwide,high-speedTTLinterfaces.

Features

nnnnnnnnnnnnn

20to85MHzshiftclocksupport

50%dutycycleonreceiveroutputclock2.5/0nsSet&HoldTimesonTxINPUTsLowpowerconsumption

±1Vcommon-moderange(around+1.2V)NarrowbusreducescablesizeandcostUpto2.38Gbpsthroughput

Upto297.5Mbytes/secbandwidth

345mV(typ)swingLVDSdevicesforlowEMIPLLrequiresnoexternalcomponentsRisingedgedatastrobe

CompatiblewithTIA/EIA-4LVDSstandardLowprofile56-leadTSSOPpackage

BlockDiagrams

DS90CR287

DS90CR288A

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10108727

OrderNumberDS90CR287MTDSeeNSPackageNumberMTD56

OrderNumberDS90CR288AMTDSeeNSPackageNumberMTD56

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DS90CR287/DS90CR288APinDiagramforTSSOPPackages

DS90CR287

DS90CR288A

1010872110108722

TypicalApplication

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DS90CR287/DS90CR288AAbsoluteMaximumRatings(Note1)

IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.SupplyVoltage(VCC)CMOS/TTLInputVoltageCMOS/TTLOutputVoltageLVDSReceiverInputVoltageLVDSDriverOutputVoltageLVDSOutputShortCircuitDuration

JunctionTemperatureStorageTemperatureLeadTemperature(Soldering,4sec.)SolderReflowTemperature

MaximumPackagePowerDissipation@+25˚CMTD56(TSSOP)Package:DS90CR287MTDDS90CR288AMTD

1.63W1.61W+260˚CContinuous

+150˚C

−65˚Cto+150˚C

−0.3Vto+4V

−0.5Vto(VCC+0.3V)−0.3Vto(VCC+0.3V)−0.3Vto(VCC+0.3V)−0.3Vto(VCC+0.3V)

PackageDerating:DS90CR287MTDDS90CR288AMTDESDRating

(HBM,1.5kΩ,100pF)(EIAJ,0Ω,200pF)LatchUpTolerance@+25˚C

12.5mW/˚Cabove+25˚C12.4mW/˚Cabove+25˚C

>7kV>700V>±300mA

RecommendedOperatingConditions

MinNomMaxUnits

SupplyVoltage(VCC)OperatingFreeAirTemperature(TA)ReceiverInputRangeSupplyNoiseVoltage(VCC)

−10+25+700

2.4

˚CV

3.0

3.3

3.6

V

100mVPPElectricalCharacteristics

OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolVIHVILVOHVOLVCLIINIOSVOD∆VODVOS∆VOSIOSIOZVTHVTLIINParameter

HighLevelInputVoltageLowLevelInputVoltageHighLevelOutputVoltageLowLevelOutputVoltageInputClampVoltageInputCurrent

OutputShortCircuitCurrentDifferentialOutputVoltageChangeinVODbetween

ComplimentaryOutputStatesOffsetVoltage(Note4)ChangeinVOSbetween

ComplimentaryOutputStatesOutputShortCircuitCurrentOutputTRI-STATECurrentDifferentialInputHighThresholdDifferentialInputLowThresholdInputCurrent

VIN=+2.4V,VCC=3.6VVIN=0V,VCC=3.6VVOUT=0V,RL=100Ω

PWRDWN=0V,VOUT=0VorVCCVCM=+1.2V

−100

−3.5

1.125

1.25

IOH=−0.4mAIOL=2mAICL=−18mA

VIN=0.4V,2.5VorVCCVIN=GNDVOUT=0VRL=100Ω

250

LVDSDRIVERDCSPECIFICATIONS

290

450351.37535−5

mVmVVmVmAµAmVmVµAµA

−10

Conditions

Min2.0GND2.7

3.30.06−0.79+1.80−60

−1200.3−1.5+15

Typ

MaxVCC0.8

UnitsVVVVVµAµAmA

LVCMOS/LVTTLDCSPECIFICATIONS

±1±10

+100

LVDSRECEIVERDCSPECIFICATIONS

±10±10

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DS90CR287/DS90CR288AElectricalCharacteristics

SymbolICCTWParameter

TRANSMITTERSUPPLYCURRENT

(Continued)

Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified

Conditions

RL=100Ω,CL=5pF,WorstCasePattern

(Figures1,2)

f=33MHzf=40MHzf=66MHzf=85MHz

Min

Typ3132374210

Max4550556055

UnitsmAmAmAmAµA

TransmitterSupplyCurrentWorstCase(withLoads)

ICCTZTransmitterSupplyCurrentPowerDown

PWRDWN=Low

DriverOutputsinTRI-STATEunderPowerdownModeCL=8pF,WorstCasePattern

(Figures1,3)

f=33MHzf=40MHzf=66MHzf=85MHz

RECEIVERSUPPLYCURRENTICCRWReceiverSupplyCurrentWorstCase

49538196140

7075114135400

mAmAmAmAµA

ICCRZReceiverSupplyCurrentPowerDown

PWRDWN=Low

ReceiverOutputsStayLowduringPowerdownMode

Note1:“AbsoluteMaximumRatings”arethosevaluesbeyondwhichthesafetyofthedevicecannotbeguaranteed.Theyarenotmeanttoimplythatthedeviceshouldbeoperatedattheselimits.Thetablesof“ElectricalCharacteristics”specifyconditionsfordeviceoperation.Note2:TypicalvaluesaregivenforVCC=3.3VandTA=+25˚C.

Note3:Currentintodevicepinsisdefinedaspositive.Currentoutofdevicepinsisdefinedasnegative.Voltagesarereferencedtogroundunlessotherwisespecified(exceptVODand∆VOD).Note4:VOSpreviouslyreferredasVCM.

TransmitterSwitchingCharacteristics

OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolLLHTLHLTTCITTPPos0TPPos1TPPos2TPPos3TPPos4TPPos5TPPos6TCIPTCIHTCILTSTCTHTCTCCDTPLLSTPDDTJIT

Parameter

LVDSLow-to-HighTransitionTime(Figure2)LVDSHigh-to-LowTransitionTime(Figure2)TxCLKINTransitionTime(Figure4)

TransmitterOutputPulsePositionforBit0(Figure14)TransmitterOutputPulsePositionforBit1TransmitterOutputPulsePositionforBit2TransmitterOutputPulsePositionforBit3TransmitterOutputPulsePositionforBit4TransmitterOutputPulsePositionforBit5TransmitterOutputPulsePositionforBit6TxCLKINPeriod(Figure5)TxCLKINHighTime(Figure5)TxCLKINLowTime(Figure5)TxINSetuptoTxCLKIN(Figure5)TxINHoldtoTxCLKIN(Figure5)TxCLKINtoTxCLKOUTDelay(Figure7)TransmitterPhaseLockLoopSet(Figure9)TransmitterPowerdownDelay(Figure12)

TxCLKINCycle-to-CycleJitter(Inputclockrequirement)

TA=25˚C,VCC=3.3Vf=85MHzf=85MHz

1.0−0.201.483.1.846.528.209.8811.760.35T0.35T2.503.8

6.3101002

01.683.365.046.728.4010.08T0.5T0.5T

Min

Typ0.750.75

Max1.51.56.00.201.883.565.246.928.6010.28500.65T0.65T

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsnsns

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DS90CR287/DS90CR288AReceiverSwitchingCharacteristics

OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolCLHTCHLTRSPos0RSPos1RSPos2RSPos3RSPos4RSPos5RSPos6RSKMRCOPRCOHRCOLRSRCRHRCRCCDRPLLSRPDD

Parameter

CMOS/TTLLow-to-HighTransitionTime(Figure3)CMOS/TTLHigh-to-LowTransitionTime(Figure3)ReceiverInputStrobePositionforBit0(Figure15)ReceiverInputStrobePositionforBit1ReceiverInputStrobePositionforBit2ReceiverInputStrobePositionforBit3ReceiverInputStrobePositionforBit4ReceiverInputStrobePositionforBit5ReceiverInputStrobePositionforBit6RxINSkewMargin(Note5)(Figure16)RxCLKOUTPeriod(Figure6)RxCLKOUTHighTime(Figure6)RxCLKOUTLowTime(Figure6)RxOUTSetuptoRxCLKOUT(Figure6)RxOUTHoldtoRxCLKOUT(Figure6)

RxCLKINtoRxCLKOUTDelay@25˚C,VCC=3.3V(Note6)(Figure8)ReceiverPhaseLockLoopSet(Figure10)ReceiverPowerdownDelay(Figure13)

f=85MHzf=85MHzf=85MHz

0.492.173.855.537.218.10.5729011.73.53.53.55.5

7

9.5101

T55

506.56

Min

Typ21.80.842.524.205.887.569.2410.92

Max3.53.51.192.874.556.237.919.5911.27

Unitsnsnsnsnsnsnsnsnsnspsnsnsnsnsnsnsmsµs

Note5:ReceiverSkewMarginisdefinedasthevaliddatasamplingregionatthereceiverinputs.Thismargintakesintoaccountthetransmitterpulsepositions(minandmax)andthereceiverinputsetupandholdtime(internaldatasamplingwindow-RSPOS).ThismarginallowsLVDSinterconnectskew,inter-symbolinterference(bothdependentontype/lengthofcable),andsourceclock(lessthan150ps).

Note6:Totallatencyforthechannellinkchipsetisafunctionofclockperiodandgatedelaysthroughthetransmitter(TCCD)andreceiver(RCCD).Thetotallatencyforthe217/287transmitterand218/288Areceiveris:(T+TCCD)+(2*T+RCCD),whereT=Clockperiod.

ACTimingDiagrams

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FIGURE1.“WorstCase”TestPattern

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DS90CR287/DS90CR288AACTimingDiagrams

(Continued)

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10108704

FIGURE2.DS90CR287(Transmitter)LVDSOutputLoadandTransitionTimes

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10108706

FIGURE3.DS90CR288A(Receiver)CMOS/TTLOutputLoadandTransitionTimes

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FIGURE4.DS90CR287(Transmitter)InputClockTransitionTime

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FIGURE5.DS90CR287(Transmitter)Setup/HoldandHigh/LowTimes

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DS90CR287/DS90CR288AACTimingDiagrams

(Continued)

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FIGURE6.DS90CR288A(Receiver)Setup/HoldandHigh/LowTimes

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FIGURE7.DS90CR287(Transmitter)ClockIntoClockOutDelay

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FIGURE8.DS90CR288A(Receiver)ClockIntoClockOutDelay

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FIGURE9.DS90CR287(Transmitter)PhaseLockLoopSetTime

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DS90CR287/DS90CR288AACTimingDiagrams

(Continued)

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FIGURE10.DS90CR288A(Receiver)PhaseLockLoopSetTime

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FIGURE11.28ParallelTTLDataInputsMappedtoLVDSOutputs

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FIGURE12.TransmitterPowerdownDelay

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DS90CR287/DS90CR288AACTimingDiagrams

(Continued)

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FIGURE13.ReceiverPowerdownDelay

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FIGURE14.TransmitterLVDSOutputPulsePositionMeasurement

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DS90CR287/DS90CR288AACTimingDiagrams

(Continued)

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FIGURE15.ReceiverLVDSInputStrobePosition

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DS90CR287/DS90CR288AACTimingDiagrams

(Continued)

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C—SetupandHoldTime(Internaldatasamplingwindow)definedbyRspos(receiverinputstrobeposition)minandmaxTppos—Transmitteroutputpulseposition(minandmax)

RSKM≥CableSkew(type,length)+SourceClockJitter(cycletocycle)(Note7)+ISI(Inter-symbolinterference)(Note8)CableSkew—typically10ps–40psperfoot,mediadependentNote7:Cycle-to-cyclejitterislessthan150psat85MHz.Note8:ISIisdependentoninterconnectlength;maybezero

FIGURE16.ReceiverLVDSInputSkewMargin

DS90CR287MTD56(TSSOP)PackagePinDescription—ChannelLinkTransmitter

PinNameTxINTxOUT+TxOUT−TxCLKINTxCLKOUT+TxCLKOUT−PWRDOWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGND

I/OIOOIOOIIIIIII

No.28441111451213

TTLlevelinput.

PositiveLVDSdifferentialdataoutput.NegativeLVDSdifferentialdataoutput.

TTLlevelclockinput.Therisingedgeactsasdatastrobe.PinnameTxCLKIN.SeeApplicationsInformationsection.PositiveLVDSdifferentialclockoutput.NegativeLVDSdifferentialclockoutput.

TTLlevelinput.Assertion(lowinput)TRI-STATEStheoutputs,ensuringlowcurrentatpowerdown.SeeApplicationsInformationsection.PowersupplypinsforTTLinputs.GroundpinsforTTLinputs.PowersupplypinforPLL.GroundpinsforPLL.

PowersupplypinforLVDSoutputs.GroundpinsforLVDSoutputs.

Description

DS90CR288AMTD56(TSSOP)PackagePinDescription—ChannelLinkReceiver

PinNameRxIN+RxIN−RxOUTRxCLKIN+RxCLKIN−RxCLKOUTPWRDOWNVCCI/OIIOIIOII

No.442811114

PositiveLVDSdifferentialdatainputs.NegativeLVDSdifferentialdatainputs.TTLleveldataoutputs.

PositiveLVDSdifferentialclockinput.NegativeLVDSdifferentialclockinput.

TTLlevelclockoutput.Therisingedgeactsasdatastrobe.PinnameRxCLKOUT.TTLlevelinput.Whenasserted(lowinput)thereceiveroutputsarelow.PowersupplypinsforTTLoutputs.

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Description

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DS90CR287/DS90CR288ADS90CR288AMTD56(TSSOP)PackagePinDescription—ChannelLinkReceiver(Continued)

PinNameGNDPLLVCCPLLGNDLVDSVCCLVDSGND

I/OIIIII

No.51213

GroundpinsforTTLoutputs.PowersupplyforPLL.GroundpinforPLL.

PowersupplypinforLVDSinputs.GroundpinsforLVDSinputs.

Description

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DS90CR287/DS90CR288AApplicationsInformation

TheTSSOPversionoftheDS90CR287andDS90CR288Aarebackwardcompatiblewiththeexisting5VChannelLinktransmitter/receiverpair(DS90CR283,DS90CR284).Toup-gradefroma5Vtoa3.3Vsystemthefollowingmustbeaddressed:1.

Change5Vpowersupplyto3.3V.ProvidethissupplytotheVCC,LVDSVCCandPLLVCC.

2.Transmitterinputandcontrolinputsexcept3.3VTTL/

CMOSlevels.Theyarenot5Vtolerant.3.

Thereceiverpowerdownfeaturewhenenabledwilllockreceiveroutputtoalogiclow.

TheChannelLinkdevicesareintendedtobeusedinawidevarietyofdatatransmissionapplications.Dependingupontheapplicationtheinterconnectingmediamayvary.Forexample,forlowerdatarate(clockrate)andshortercablelengths(<2m),themediaelectricalperformanceislesscritical.Forhigherspeed/longdistanceapplicationstheme-dia’sperformancebecomesmorecritical.Certaincablecon-structionsprovidetighterskew(matchedelectricallengthbetweentheconductorsandpairs).AdditionalapplicationsinformationcanbefoundinthefollowingNationalInterfaceApplicationNotes:AN=####AN-1041AN-1108AN-806AN-905AN-916

Topic

IntroductiontoChannelLinkChannelLinkPCBandInterconnectDesign-InGuidelinesTransmissionLineTheory

TransmissionLineCalculationsandDifferentialImpedanceCableInformation

Thehigh-speedtransportofLVDSsignalshasbeendemon-stratedonseveraltypesofcableswithexcellentresults.However,thebestoverallperformancehasbeenseenwhenusingTwin-Coaxcable.Twin-CoaxhasverylowcableskewandEMIduetoitsconstructionanddoubleshielding.Allofthedesignconsiderationsdiscussedhereandlistedinthesupplementalapplicationnotesprovidethesubsystemcom-municationsdesignerwithmanyusefulguidelines.Itisrec-ommendedthatthedesignerassessthetradeoffsofeachapplicationthoroughlytoarriveatareliableandeconomicalcablesolution.

RECEIVERFAILSAFEFEATURE:Thesereceivershaveinputfailsafebiascircuitrytoguaranteeastablereceiveroutputforfloatingorterminatedreceiverinputs.UndertheseconditionsreceiverinputswillbeinaHIGHstate.Ifaclocksignalispresent,dataoutputswillallbeHIGH;iftheclockinputisalsofloating/terminated,dataoutputswillremaininthelastvalidstate.Afloating/terminatedclockinputwillresultinaHIGHclockoutput.

BOARDLAYOUT:ToobtainthemaximumbenefitfromthenoiseandEMIreductionsofLVDS,attentionshouldbepaidtothelayoutofdifferentiallines.Linesofadifferentialpairshouldalwaysbeadjacenttoeliminatenoiseinterferencefromothersignalsandtakefulladvantageofthenoisecancelingofthedifferentialsignals.Theboarddesignershouldalsotrytomaintainequallengthonsignaltracesforagivendifferentialpair.Aswithanyhigh-speeddesign,theimpedancediscontinuitiesshouldbelimited(reducethenumbersofviasandno90degreeanglesontraces).Anydiscontinuitieswhichdooccurononesignallineshouldbemirroredintheotherlineofthedifferentialpair.Careshouldbetakentoensurethatthedifferentialtraceimpedancematchthedifferentialimpedanceoftheselectedphysicalmedia(thisimpedanceshouldalsomatchthevalueoftheterminationresistorthatisconnectedacrossthedifferentialpairatthereceiver’sinput).Finally,thelocationoftheCHANNELLINKTxOUT/RxINpinsshouldbeascloseaspossibletotheboardedgesoastoeliminateexcessivepcbruns.AlloftheseconsiderationswilllimitreflectionsandcrosstalkwhichadverselyeffecthighfrequencyperformanceandEMI.

INPUTS:TheTxINandcontrolpininputsarecompatiblewithLVTTLandLVCMOSlevels.Thispinsarenot5Vtoler-ant.

UNUSEDINPUTS:AllunusedinputsattheTxINinputsofthetransmittermaybetiedtogroundorleftnoconnect.AllunusedoutputsattheRxOUToutputsofthereceivermustthenbeleftfloating.

TERMINATION:Useofcurrentmodedriversrequiresaterminatingresistoracrossthereceiverinputs.TheCHAN-NELLINKchipsetwillnormallyrequireasingle100Ωresistorbetweenthetrueandcomplementlinesoneachdifferentialpairofthereceiverinput.Theactualvalueoftheterminationresistorshouldbeselectedtomatchthedifferentialmodecharacteristicimpedance(90Ωto120Ωtypical)ofthecable.Figure17showsanexample.Noadditionalpull-uporpull-downresistorsarenecessaryaswithsomeotherdifferentialtechnologiessuchasPECL.Surfacemountresistorsarerecommendedtoavoidtheadditionalinductancethatac-companiesleadedresistors.Theseresistorsshouldbeplacedascloseaspossibletothereceiverinputpinstoreducestubsandeffectivelyterminatethedifferentiallines.DECOUPLINGCAPACITORS:Bypassingcapacitorsareneededtoreducetheimpactofswitchingnoisewhichcouldlimitperformance.Foraconservativeapproachthreeparallel-connecteddecouplingcapacitors(Multi-LayeredCe-13

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CABLES:AcableinterfacebetweenthetransmitterandreceiverneedstosupportthedifferentialLVDSpairs.The21-bitCHANNELLINKchipset(DS90CR217/218A)requiresfourpairsofsignalwiresandthe28-bitCHANNELLINKchipset(DS90CR287/288A)requiresfivepairsofsignalwires.Theidealcable/connectorinterfacewouldhaveaconstant100Ωdifferentialimpedancethroughoutthepath.Itisalsorecommendedthatcableskewremainbelow140ps(@85MHzclockrate)tomaintainasufficientdatasamplingwindowatthereceiver.

Inadditiontothefourorfivecablepairsthatcarrydataandclock,itisrecommendedtoprovideatleastoneadditionalconductor(orpair)whichconnectsgroundbetweenthetransmitterandreceiver.Thislowimpedancegroundpro-videsacommon-modereturnpathforthetwodevices.Someofthemorecommonlyusedcabletypesforpoint-to-pointapplicationsincludeflatribbon,flex,twistedpairandTwin-Coax.Allareavailableinavarietyofconfigurationsandoptions.Flatribboncable,flexandtwistedpairgenerallyperformwellinshortpoint-to-pointapplicationswhileTwin-Coaxisgoodforshortandlongapplications.Whenusingribboncable,itisrecommendedtoplaceagroundlinebetweeneachdifferentialpairtoactasabarriertonoisecouplingbetweenadjacentpairs.ForTwin-Coaxcableap-plications,itisrecommendedtoutilizeashieldoneachcablepair.Allextendedpoint-to-pointapplicationsshouldalsoemployanoverallshieldsurroundingallcablepairsregardlessofthecabletype.Thisoverallshieldresultsinimprovedtransmissionparameterssuchasfasterattainablespeeds,longerdistancesbetweentransmitterandreceiverandreducedproblemsassociatedwithEMSorEMI.

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DS90CR287/DS90CR288AApplicationsInformation

(Continued)

ramictypeinsurfacemountformfactor)betweeneachVCCandthegroundplane(s)arerecommended.Thethreeca-pacitorvaluesare0.1µF,0.01µFand0.001µF.AnexampleisshowninFigure18.Thedesignershouldemploywide

tracesforpowerandgroundandensureeachcapacitorhasitsownviatothegroundplane.Ifboardspaceislimitingthenumberofbypasscapacitors,thePLLVCCshouldreceivethemostfiltering/bypassing.NextwouldbetheLVDSVCCpinsandfinallythelogicVCCpins.

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FIGURE17.LVDSSerializedLinkTermination

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FIGURE18.CHANNELLINKDecouplingConfiguration

CLOCKJITTER:TheCHANNELLINKdevicesemployaPLLtogenerateandrecovertheclocktransmittedacrosstheLVDSinterface.ThewidthofeachbitintheserializedLVDSdatastreamisone-sevenththeclockperiod.Forexample,a85MHzclockhasaperiodof11.76nswhichresultsinadatabitwidthof1.68ns.Differentialskew(∆twithinonedifferen-tialpair),interconnectskew(∆tofonedifferentialpairtoanother)andclockjitterwillallreducetheavailablewindowforsamplingtheLVDSserialdatastreams.Caremustbetakentoensurethattheclockinputtothetransmitterbeacleanlownoisesignal.IndividualbypassingofeachVCCtogroundwillminimizethenoisepassedontothePLL,thuscreatingalowjitterLVDSclock.Thesemeasuresprovidemoremarginforchannel-to-channelskewandinterconnectskewasapartoftheoveralljitter/skewbudget.

INPUTCLOCK:Theinputclockshouldbepresentatalltimeswhenthepartinenabled.Iftheclockisstopped,thePWRDOWNpinshouldbeassertedtodisablethePLL.Oncetheclockisactiveagain,thepartcanthenbeenabled.Donotenablethepartwithoutaclockpresent.

COMMON-MODEvs.DIFFERENTIALMODENOISEMAR-GIN:ThetypicalsignalswingforLVDSis300mVcenteredat+1.2V.TheCHANNELLINKreceiversupportsa100mVthresholdthereforeprovidingapproximately200mVofdif-ferentialnoisemargin.Common-modeprotectionisofmoreimportancetothesystem’soperationduetothedifferential

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datatransmission.LVDSsupportsaninputvoltagerangeofGroundto+2.4V.Thisallowsfora±1.0Vshiftingofthecenterpointduetogroundpotentialdifferencesandcommon-modenoise.

TRANSMITTERINPUTCLOCK:Thetransmitterinputclockmustalwaysbepresentwhenthedeviceisenabled(PWRDOWN=HIGH).Iftheclockisstopped,thePWRDOWNpinmustbeusedtodisablethePLL.ThePWRDOWNpinmustbeheldlowuntilaftertheinputclocksignalhasbeenreap-plied.ThiswillensureaproperdeviceresetandPLLlocktooccur.

POWERSEQUENCINGANDPOWERDOWNMODE:Out-putsoftheCHANNELLINKtransmitterremaininTRI-STATEuntilthepowersupplyreaches2V.Clockanddataoutputswillbegintotoggle10msafterVCChasreached3VandthePowerdownpinisabove1.5V.EitherdevicemaybeplacedintoapowerdownmodeatanytimebyassertingthePow-erdownpin(activelow).Totalpowerdissipationforeachdevicewilldecreaseto5µW(typical).

Thetransmitterinputclockmaybeappliedpriortopoweringupandenablingthetransmitter.Thetransmitterinputclockmayalsobeappliedafterpowerup;however,theuseofthePWRDOWNpinisrequiredasdescribedintheTransmitter

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DS90CR287/DS90CR288AApplicationsInformation

(Continued)

InputClocksection.Donotpowerupandenable(PWRDOWN=HIGH)thetransmitterwithoutavalidclocksignalappliedtotheTxCLKINpin.

TheCHANNELLINKchipsetisdesignedtoprotectitselffromaccidentallossofpowertoeitherthetransmitteror

receiver.Ifpowertothetransmitboardislost,thereceiverclocks(inputandoutput)stop.Thedataoutputs(RxOUT)retainthestatestheywereinwhentheclocksstopped.Whenthereceiverboardlosespower,thereceiverinputsareshortedtoVCCthroughaninternaldiode.Currentislimited(5mAperinput)bythefixedcurrentmodedrivers,thusavoidingthepotentialforlatchupwhenpoweringthedevice.

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FIGURE19.Single-EndedandDifferentialWaveforms

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DS90CR287/DS90CR288A+3.3VRisingEdgeDataStrobeLVDS28-BitChannelLink-85MHzPhysicalDimensions

unlessotherwisenoted

inches(millimeters)

56-LeadMoldedThinShrinkSmalloutlinePackage,JEDEC

OrderNumberDS90CR287MTDorDS90CR288AMTD

Dimensionsshowninmillimetersonly

NSPackageNumberMTD56

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