SN74CB3T338410ĆBIT FET BUS SWITCH2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTERSCDS159B − OCTOBER 2003 − REVISED MARCH 2004DOutput Voltage Translation Tracks VCCDSupports Mixed-Mode Signal Operation OnAll Data I/O Ports− 5-V Input Down To 3.3-V Output LevelShift With 3.3-V VCC− 5-V/3.3-V Input Down To 2.5-V OutputLevel Shift With 2.5-V VCC5-V-Tolerant I/Os With Device Powered-Upor Powered-DownBidirectional Data Flow, With Near-ZeroPropagation DelayLow ON-State Resistance (ron)Characteristics (ron = 5 Ω Typical)Low Input/Output Capacitance MinimizesLoading (Cio(OFF) = 5 pF Typical)Data and Control Inputs ProvideUndershoot Clamp DiodesLow Power Consumption(ICC = 40 µA Max)DVCC Operating Range From 2.3 V to 3.6 VDData I/Os Support 0 to 5-V Signaling LevelsDDDDDDDDDDDD(For Example: 0.8-V, 1.2-V, 1.5-V, 1.8-V,2.5-V, 3.3-V, 5-V)Control Inputs Can Be Driven by TTL or5-V/3.3-V/2.5-V CMOS OutputsIoff Supports Partial-Power-Down ModeOperationLatch-Up Performance Exceeds 250 mA PerJESD 17ESD Performance Tested Per JESD 22− 2000-V Human-Body Model(A114-B, Class II)− 1000-V Charged-Device Model (C101)Supports Digital Applications: LevelTranslation, Memory Interleaving, BusIsolationIdeal for Low-Power Portable EquipmentDBQ, DGV, DW, OR PW PACKAGE(TOP VIEW)1OE1B11A11A21B21B31A31A41B41B51A5GND1234567101112242322212019181716151413VCC2B52A52A42B42B32A32A22B22B12A12OEdescription/ordering informationORDERING INFORMATIONTASOIC − DW−40°C to 85°CSSOP (QSOP) − DBQTSSOP − PWTVSOP − DGVPACKAGE†TubeTape and reelTape and reelTubeTape and reelTape and reelORDERABLEPART NUMBERSN74CB3T3384DWSN74CB3T3384DWRSN74CB3T3384DBQRSN74CB3T3384PWSN74CB3T3384PWRSN74CB3T3384DGVRTOP-SIDEMARKINGCB3T3384CB3T3384KS384†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines areavailable at www.ti.com/sc/package.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright 2004, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1芯天下--http://oneic.com/SCDS159B − OCTOBER 2003 − REVISED MARCH 2004SN74CB3T338410ĆBIT FET BUS SWITCH2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTERdescription/ordering information (continued)The SN74CB3T3384 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/Oports by providing voltage translation that tracks VCC. The SN74CB3T3384 supports systems using 5-V TTL,3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).VCC5.5 VVCC≈VCC − 1 VINOUT≈VCC≈VCC − 1 VCB3T0 V0 VInput VoltagesOutput VoltagesNOTE A:If the input high voltage (VIH) level is greater than or equal to VCC − 1 V, and less than or equal to 5.5 V, the output highvoltage (VOH) level will be equal to approximately the VCC voltage level.Figure 1. Typical DC-Voltage-Translation CharacteristicsThe SN74CB3T3384 is organized as two 5-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. Itcan be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit busswitch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. WhenOE is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures thatdamaging current will not backflow through the device when it is powered down. The device has isolation duringpower off.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.FUNCTION TABLE(each 5-bit bus switch)INPUTOELHINPUT/OUTPUTABZFUNCTIONA port = B portDisconnect2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/SN74CB3T338410ĆBIT FET BUS SWITCH2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTERSCDS159B − OCTOBER 2003 − REVISED MARCH 2004logic diagram (positive logic)1A13SW21B11A511SW101B51OE12A114SW152B12A522SW232B52OE13simplified schematic, each FET switch (SW)†Gate Voltage (VG) is approximatelyequal to VCC + VT when the switch is ONand VI > VCC + VT.AVG†ControlCircuitBEN‡‡EN is the internal enable signal applied to the switch.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3芯天下--http://oneic.com/SCDS159B − OCTOBER 2003 − REVISED MARCH 2004SN74CB3T338410ĆBIT FET BUS SWITCH2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTERabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 VControl input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 VSwitch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 VControl input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mAI/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mAON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mAContinuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mAPackage thermal impedance, θJA (see Note 5):DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/WDGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/WDW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/WPW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/WStorage temperature range, Tstg −65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.All voltages are with respect to ground unless otherwise specified.2.The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.3.VI and VO are used to denote specific conditions for VI/O.4.II and IO are used to denote specific conditions for II/O.5.The package thermal impedance is calculated in accordance with JESD 51-7.recommended operating conditions (see Note 6)MINVCCVIHVILVI/OTASupply voltageHigh-level control input voltageLow-level control input voltageData input/output voltageOperating free-air temperatureVCC = 2.3 V to 2.7 VVCC = 2.7 V to 3.6 VVCC = 2.3 V to 2.7 VVCC = 2.7 V to 3.6 V2.31.72000−40MAX3.65.55.50.70.85.585UNITVVVV°CNOTE 6:All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/SN74CB3T338410ĆBIT FET BUS SWITCH2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTERSCDS159B − OCTOBER 2003 − REVISED MARCH 2004electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERVIKVOHIINControl inputsVCC = 3 V,II = −18 mASee Figures 3 and 4VCC = 3.6 V,VIN = 3.6 V to 5.5 V or GNDVCC = 3.6 V,Switch ON,VIN = GNDVCC = 3.6 V,VO = 0 to 5.5 V,VI = 0,Switch OFF,VIN = VCCVCC = 0,VO = 0 to 5.5 V,VI = 0VCC = 3.6 V,II/O = 0,Switch ON or OFF,VIN = VCC or GNDVCC = 3 V to 3.6 V,One input at VCC − 0.6 V,Other inputs at VCC or GNDVCC = 3.3 V,VIN = VCC or GNDVCC = 3.3 V,VI/O = 5.5 V, 3.3 V, or GND,Switch OFF,VIN = VCCVCC = 3.3 V,Switch ON,VIN = GNDVCC = 2.3 V,TYP at VCC = 2.5 V,VI = 0VCC = 3 V,VI = 0VI/O = 5.5 V or 3.3 VVI/O = GNDIO = 24 mAIO = 16 mAIO = mAIO = 32 mAVI = VCC or GNDVI = 5.5 VVI = VCC − 0.7 V to 5.5 VVI = 0.7 V to VCC − 0.7 VVI = 0 to 0.7 V±10±20−40±5µAµATEST CONDITIONSMINTYP†MAX−1.2UNITVIIIOZ‡±10µAIoff1040µAICCµA40300µA∆ICC§CinControl inputsControl inputs3pFCio(OFF)5pF41255558877ΩpFCio(ON)ron¶VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.†All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.‡For I/O ports, the parameter IOZ includes the input leakage current.§This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.¶Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by thelower of the voltages of the two (A or B) terminals.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5芯天下--http://oneic.com/SCDS159B − OCTOBER 2003 − REVISED MARCH 2004SN74CB3T338410ĆBIT FET BUS SWITCH2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTERswitching characteristics over recommended operating free-air temperature range (unlessotherwise noted) (see Figure 2)PARAMETERtpd†tenFROM(INPUT)A or BOETO(OUTPUT)B or AA or B1VCC = 2.5 V± 0.2 VMINMAX0.1510.51VCC = 3.3 V± 0.3 VMINMAX0.257.5nsnsUNITtdisOEA or B16.518ns†The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,when driven by an ideal voltage source (zero output impedance).6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/SN74CB3T338410ĆBIT FET BUS SWITCH2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTERSCDS159B − OCTOBER 2003 − REVISED MARCH 2004PARAMETER MEASUREMENT INFORMATIONVCCInput Generator50 ΩVG150 ΩDUTInput Generator50 ΩVG250 ΩCL(see Note A)RLVIVORLS12 × VCCOpenGNDTEST CIRCUITVINTESTtPLZ/tPZLtPHZ/tPZHVCC2.5 V ±0.2 V3.3 V ±0.3 V2.5 V ±0.2 V3.3 V ±0.3 VS12 × VCC2 × VCCOpenOpenRL500 Ω500 Ω500 Ω500 ΩVIGNDGND3.6 V5.5 VCL30 pF50 pF30 pF50 pFV∆0.15 V0.3 V0.15 V0.3 VOutputControl(VIN)tPZLOutputWaveform 1S1 at 2 × VCC(see Note B)tPZHOutputWaveform 2S1 at Open(see Note B)VCCVCC/2VCC/20 VtPLZVCCVCC/2VOL + V∆tPHZVOH − V∆VOH0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESVOLVCC/2NOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.D.The outputs are measured one at a time, with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.Figure 2. Test Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7芯天下--http://oneic.com/SCDS159B − OCTOBER 2003 − REVISED MARCH 2004SN74CB3T338410ĆBIT FET BUS SWITCH2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTERTYPICAL CHARACTERISTICSOUTPUT VOLTAGEvsINPUT VOLTAGE4.0VCC = 2.3 VIO = 1 µATA = 25°C4.0VCC = 3 VIO = 1 µATA = 25°COUTPUT VOLTAGEvsINPUT VOLTAGEV − Output Voltage − VO3.0V − Output Voltage − VO2.03.04.05.06.03.02.02.01.01.00.00.01.0VI − Input Voltage − V0.00.01.02.03.04.05.06.0VI − Input Voltage − VFigure 3. Data Output Voltage vs Data Input Voltage8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/SN74CB3T338410ĆBIT FET BUS SWITCH2.5ĆV/3.3ĆV LOWĆVOLTAGE BUS SWITCH WITH 5ĆVĆTOLERANT LEVEL SHIFTERSCDS159B − OCTOBER 2003 − REVISED MARCH 2004TYPICAL CHARACTERISTICS (continued)OUTPUT VOLTAGE HIGHvsSUPPLY VOLTAGE4.0V − Output Voltage High − VOH3.53.0VCC = 2.3 V ~ 3.6 VVI = 5.5 VTA = 85°C4.0100 µA8 mA16 mA24 mAV − Output Voltage High − VOH3.53.0OUTPUT VOLTAGE HIGHvsSUPPLY VOLTAGEVCC = 2.3 V ~ 3.6 VVI = 5.5 VTA = 25°C100 µA8 mA16 mA24 mA2.52.01.52.32.52.72.93.13.3VCC − Supply Voltage − V3.53.72.52.01.52.32.52.72.93.13.33.53.7VCC − Supply Voltage − VOUTPUT VOLTAGE HIGHvsSUPPLY VOLTAGE4.0V − Output Voltage High − VOHVCC = 2.3 V to 3.6 VVI = 5.5 VTA = -40°C100 µA8 mA16 mA24 mA3.53.02.52.01.52.32.52.72.93.13.33.53.7VCC − Supply Voltage − VFigure 4. VOH ValuesPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•9芯天下--http://oneic.com/PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Orderable Device74CB3T3384DBQRE474CB3T3384DBQRG4SN74CB3T3384DBQRSN74CB3T3384DWSN74CB3T3384DWE4SN74CB3T3384DWG4SN74CB3T3384DWRSN74CB3T3384DWRE4SN74CB3T3384DWRG4SN74CB3T3384PWSN74CB3T3384PWE4SN74CB3T3384PWG4SN74CB3T3384PWRSN74CB3T3384PWRE4SN74CB3T3384PWRG4
(1)
Status
(1)
Package TypePackage
Drawing
SSOPSSOPSSOPSOICSOICSOICSOICSOICSOICTSSOPTSSOPTSSOPTSSOPTSSOPTSSOP
DBQDBQDBQDWDWDWDWDWDWPWPWPWPWPWPW
Pins242424242424242424242424242424
Package Qty
250025002500252525200020002000606060200020002000
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
Samples(Requires Login)
ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE
Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)Green (RoHS& no Sb/Br)
CU NIPDAULevel-2-260C-1 YEARCU NIPDAULevel-2-260C-1 YEARCU NIPDAULevel-2-260C-1 YEARCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIMCU NIPDAULevel-1-260C-UNLIM
The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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16-Aug-2012
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms \"Lead-Free\" or \"Pb-Free\" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines \"Green\" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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PACKAGEMATERIALSINFORMATION
www.ti.com
16-Aug-2012
TAPEANDREELINFORMATION
*Alldimensionsarenominal
Device
PackagePackagePinsTypeDrawingSSOPSOICTSSOP
DBQDWPW
242424
SPQ
ReelReelA0DiameterWidth(mm)(mm)W1(mm)330.0330.0330.0
16.424.416.4
6.510.756.95
B0(mm)9.015.78.3
K0(mm)2.12.71.6
P1(mm)8.012.08.0
WPin1(mm)Quadrant16.024.016.0
Q1Q1Q1
SN74CB3T3384DBQRSN74CB3T3384DWRSN74CB3T3384PWR
250020002000
PackMaterials-Page1
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PACKAGEMATERIALSINFORMATION
www.ti.com
16-Aug-2012
*Alldimensionsarenominal
Device
SN74CB3T3384DBQRSN74CB3T3384DWRSN74CB3T3384PWR
PackageType
SSOPSOICTSSOP
PackageDrawing
DBQDWPW
Pins242424
SPQ250020002000
Length(mm)
367.0367.0367.0
Width(mm)367.0367.0367.0
Height(mm)
38.045.038.0
PackMaterials-Page2
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