SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSSCBS120E – AUGUST 1991 – REVISED JULY 1996DMembers of the Texas InstrumentsDDDDDDSCOPE™ Family of Testability ProductsCompatible With the IEEE Standard1149.1-1990 (JTAG) Test Access Port andBoundary-Scan ArchitectureFunctionally Equivalent to ’F543 and’ABT543 in the Normal-Function ModeSCOPE™ Instruction Set– IEEE Standard 1149.1-1990 RequiredInstructions, Optional INTEST, CLAMP,and HIGHZ– Parallel-Signature Analysis at InputsWith Masking Option– Pseudo-Random Pattern GenerationFrom Outputs– Sample Inputs/Toggle Outputs– Binary Count From Outputs– Even-Parity OpcodesTwo Boundary-Scan Cells Per I/O forGreater FlexibilityState-of-the-Art EPIC-ΙΙB™ BiCMOS DesignSignificantly Reduces Power DissipationPackage Options Include PlasticSmall-Outline (DW) and ShrinkSmall-Outline (DL) Packages, Ceramic ChipCarriers (FK), and Standard CeramicDIPs (JT)SN54ABT8543...JT PACKAGESN74ABT8543...DL OR DW PACKAGE(TOP VIEW)LEABCEABOEABA1A2A3GNDA4A5A6A7A8TDOTMS123456710111213142827262524232221201918171615LEBACEBAOEBAB1B2B3B4VCCB5B6B7B8TDITCKSN54ABT8543...FK PACKAGE(TOP VIEW)B1B2B3B4VCCB5B6OEBACEBALEBALEABCEABOEABA1567104321282726252423222120111912131415161718descriptionThe ’ABT8543 scan test devices with octalregistered bus transceivers are members of theTexas Instruments SCOPE™ testabilityintegrated-circuit family. This family of devicessupports IEEE Standard 1149.1-1990 boundaryscan to facilitate testing of complex circuit-boardassemblies. Scan access to the test circuitry isaccomplished via the 4-wire test access port(TAP) interface.B7B8TDITCKTMSTDOA8In the normal mode, these devices are functionally equivalent to the ’F543 and ’ABT543 octal registered bustransceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing atthe device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does notaffect the functional operation of the SCOPE™ octal registered bus transceivers.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•A2A3GNDA4A5A6A7Copyright © 1996, Texas Instruments IncorporatedOn products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.1http://oneic.com/SCBS120E – AUGUST 1991 – REVISED JULY 1996SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSdescription (continued) Data flow in each direction is controlled by latch-enable (LEAB and LEBA), chip-enable (CEAB and CEBA), andoutput-enable (OEAB and OEBA) inputs. For A-to-B data flow, the device operates in the transparent modewhen LEAB and CEAB are both low. When either LEAB or CEAB is high, the A data is latched. The B outputsare active when OEAB and CEAB are both low. When either OEAB or CEAB is high, the B outputs are in thehigh-impedance state. Control for B-to-A data flow is similar to that for A-to-B, but uses LEBA, CEBA, and OEBA.In the test mode, the normal operation of the SCOPE™ registered bus transceiver is inhibited and the testcircuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitryperforms boundary-scan test operations as described in IEEE Standard 1149.1-1990.Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO),test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functionssuch as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) fromdata outputs. All testing and scan operations are synchronized to the TAP interface.The SN54ABT8543 is characterized for operation over the full military temperature range of –55°C to 125°C.The SN74ABT8543 is characterized for operation from –40°C to 85°C.FUNCTION TABLE†(normal mode, each register)INPUTSCEABLLLLHOEABLLLHXLEABLLHXXALHXXXOUTPUTBLHB0‡ZZ†A-to-B data flow is shown. B-to-A data flow is similar butuses CEBA, OEBA, and LEBA.‡Output level before the indicated steady-state inputconditions were established2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•http://oneic.com/ SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSSCBS120E – AUGUST 1991 – REVISED JULY 1996functional block diagramBoundary-Scan RegisterOEBACEBALEBAOEABCEABLEAB262728321C11DA14C11DOne of Eight Channels25B1Bypass RegisterBoundary-ControlRegisterVCCTDI16Instruction Register13TDOVCCTMS14TAPControllerTCK15Pin numbers shown are for the DL, DW, and JT packages.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3http://oneic.com/SCBS120E – AUGUST 1991 – REVISED JULY 1996SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSTerminal FunctionsTERMINALNAMEA1–A8B1–B8CEAB, CEBAGNDLEAB, LEBAOEAB, OEBATCKTDITDOTMSVCCDESCRIPTIONNormal-function A-bus I/O ports. See function table for normal-mode logic.Normal-function B-bus I/O ports. See function table for normal-mode logic.Normal-function chip-enable inputs. See function table for normal-mode logic.GroundNormal-function latch-enable inputs. See function table for normal-mode logic.Normal-function output-enable inputs. See function table for normal-mode logic.Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous toTCK. Data is captured on the rising edge of TCK, and outputs change on the falling edge of TCK.Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data throughthe instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting datathrough the instruction register or selected data register.Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAPcontroller states. An internal pullup forces TMS to a high level if left unconnected.Supply voltage 4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•http://oneic.com/ SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSSCBS120E – AUGUST 1991 – REVISED JULY 1996test architectureSerial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. TheTAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts thesynchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chipcontrol signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK andoutput data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fullyone-half of the TCK cycle.The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scanarchitecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, thedevice contains an 8-bit instruction register and three test-data registers: a 40-bit boundary-scan register, an11-bit boundary-control register, and a 1-bit bypass register.Test-Logic-ResetTMS = HTMS = LTMS = HRun-Test/IdleTMS = LSelect-DR-ScanTMS = LTMS = HCapture-DRTMS = LShift-DRTMS = LTMS = HTMS = HExit1-DRTMS = LPause-DRTMS = LTMS = HTMS = LExit2-DRTMS = HUpdate-DRTMS = HTMS = LTMS = LExit2-IRTMS = HUpdate-IRTMS = HTMS = LTMS = HExit1-IRTMS = LPause-IRTMS = LTMS = HTMS = HTMS = HCapture-IRTMS = LShift-IRTMS = LTMS = HSelect-IR-ScanTMS = LTMS = HFigure 1. TAP-Controller State DiagramPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5http://oneic.com/SCBS120E – AUGUST 1991 – REVISED JULY 1996SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSstate diagram description The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controllerproceeds through its states based on the level of TMS at the rising edge of TCK.As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow inthe state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutiveTCK cycles. Any state that does not meet this criterion is an unstable state.There are two main paths through the state diagram: one to access and control the selected data register andone to access and control the instruction register. Only one register can be accessed at a time.Test-Logic-ResetThe device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is resetand is disabled so that the normal logic function of the device is performed. The instruction register is reset toan opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain dataregisters also can be reset to their power-up values.The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no morethan five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if leftunconnected or if a board defect causes it to be open circuited.For the ’ABT8543, the instruction register is reset to the binary value 11111111, which selects the BYPASSinstruction. Each bit in the boundary-scan register is reset to logic 0. The boundary-control register is reset tothe binary value 00000000010, which selects the PSA test operation with no input masking.Run-Test/IdleThe TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any testoperations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle.The test operations selected by the boundary-control register are performed while the TAP controller is in theRun-Test/Idle state.Select-DR-Scan, Select-lR-ScanNo specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exitseither of these states on the next TCK cycle. These states allow the selection of either data-register scan orinstruction-register scan.Capture-DRWhen a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In theCapture-DR state, the selected data register can capture a data value as specified by the current instruction.Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits theCapture-DRstate.Shift-DRUpon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on thefirst falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logiclevel present in the least-significant bit of the selected data register.While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs duringthe TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•http://oneic.com/ SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSSCBS120E – AUGUST 1991 – REVISED JULY 1996Exit1-DR, Exit2-DRThe Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to returnto the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to thehigh-impedancestate.Pause-DRNo specific function is performed in the stable Pause-DR state, in which the TAP controller can remainindefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.Update-DRIf the current instruction calls for the selected data register to be updated with current data, then such updateoccurs on the falling edge of TCK, following entry to the Update-DR state.Capture-IRWhen an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. Inthe Capture-IR state, the instruction register captures its current status value. This capture operation occurson the rising edge of TCK, upon which the TAP controller exits the Capture-IR state.For the ’ABT8543, the status value loaded in the Capture-IR state is the fixed binary value 10000001.Shift-IRUpon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables tothe logic level present in the least-significant bit of the instruction register.While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCKcycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occursduring the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR toShift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.Exit1-IR, Exit2-IRThe Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible toreturn to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to thehigh-impedancestate.Pause-IRNo specific function is performed in the stable Pause-IR state, in which the TAP controller can remainindefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without lossofdata.Update-IRThe current instruction is updated and takes effect on the falling edge of TCK, following entry to theUpdate-IRstate.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7http://oneic.com/SCBS120E – AUGUST 1991 – REVISED JULY 1996SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSregister overview With the exception of the bypass register, any test register can be thought of as a serial-shift register with ashadow latch on each bit. The bypass register differs in that it contains only a shift register. During theappropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift registercan be parallel loaded from a source specified by the current instruction. During the appropriate shift state(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shiftedin at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated fromthe shift register.instruction register descriptionThe instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Informationcontained in the instruction includes the mode of operation (either normal mode, in which the device performsits normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operationto be performed, which of the three data registers is to be selected for inclusion in the scan path duringdata-register scans, and the source of data to be captured into the selected data register during Capture-DR.Table 3 lists the instructions supported by the ’ABT8543. The even-parity feature specified for SCOPE™ devicesis supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined forSCOPE™ devices but are not supported by this device default to BYPASS.During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shiftedout via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the valuethat has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated,and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to thebinary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2.TDIBit 7Parity(MSB)Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0(LSB)TDOFigure 2. Instruction Register Order of Scandata register descriptionboundary-scan registerThe boundary-scan register (BSR) is 40 bits long. It contains one boundary-scan cell (BSC) for eachnormal-function input pin, two BSCs for each normal-function I/O pin (one for input data and one for output data),and one BSC for each of the internally decoded output-enable signals (OEA and OEB). The BSR is used to storetest data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the deviceoutput pins, and/or to capture data that appears internally at the outputs of the normal on-chip logic and/orexternally at the device input pins.The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. Thecontents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up orin Test-Logic-Reset, the value of each BSC is reset to logic 0.When external data is to be captured, the BSCs for signals OEA and OEB capture logic values determined bythe following positive-logic equations: OEA+OEBA)CEBA,andOEB+OEAB)CEAB. When data is tobe applied externally, these BSCs control the drive state (active or high-impedance) of their respective outputs.The BSR order of scan is from TDI through bits 39–0 to TDO. Table 1 shows the BSR bits and their associateddevice pin signals.8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•http://oneic.com/ SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSSCBS120E – AUGUST 1991 – REVISED JULY 1996Table 1. Boundary-Scan Register ConfigurationBSR BITNUMBER3938373635343332DEVICESIGNALOEBOEAOEABOEBALEABLEBACEABCEBABSR BITNUMBER3130292827262524DEVICESIGNALA8-IA7-IA6-IA5-IA4-IA3-IA2-IA1-IBSR BITNUMBER2322212019181716DEVICESIGNALA8-OA7-OA6-OA5-OA4-OA3-OA2-OA1-OBSR BITNUMBER15141312111098DEVICESIGNALB8-IB7-IB6-IB5-IB4-IB3-IB2-IB1-IBSR BITNUMBER76543210DEVICESIGNALB8-OB7-OB6-OB5-OB4-OB3-OB2-OB1-Oboundary-control registerThe boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction toimplement additional test operations not included in the basic SCOPE™ instruction set. Such operations includePRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations that aredecoded by the BCR.During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR isreset to the binary value 00000000010, which selects the PSA test operation with no input masking.The BCR order of scan is from TDI through bits 10–0 to TDO. Table 2 shows the BCR bits and their associatedtest control signals.Table 2. Boundary-Control Register ConfigurationBCR BITNUMBER10987TESTCONTROLSIGNALMASK8MASK7MASK6MASK5BCR BITNUMBER6543TESTCONTROLSIGNALMASK4MASK3MASK2MASK1BCR BITNUMBER210––TESTCONTROLSIGNALOPCODE2OPCODE1OPCODE0––bypass registerThe bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,thereby reducing the number of bits per test pattern that must be applied to complete a test operation. DuringCapture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 3.TDIBit 0TDOFigure 3. Bypass Register Order of ScanPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•9http://oneic.com/SCBS120E – AUGUST 1991 – REVISED JULY 1996SN54ABT8543, SN74ABT8543SCAN TEST DEVICES WITHOCTAL REGISTERED BUS TRANSCEIVERSinstruction-register opcode description The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation ofeach instruction.Table 3. Instruction-Register OpcodesBINARY CODE†BIT 7→ BIT 0MSB → LSB00000000100000011000001000000011100001000000010100000110100001111000100000001001000010101000101100001100100011011000111000001111All othersSCOPE OPCODEEXTEST/INTESTBYPASS‡SAMPLE/PRELOADINTEST/EXTESTBYPASS‡BYPASS‡HIGHZCLAMPBYPASS‡RUNTREADBNREADBTCELLTSTTOPHIPSCANCNSCANCTBYPASSDESCRIPTIONBoundary scanBypass scanSample boundaryBoundary scanBypass scanBypass scanControl boundary to high impedanceControl boundary to 1/0Bypass scanBoundary run testBoundary readBoundary readBoundary self testBoundary toggle outputsBoundary-control register scanBoundary-control register scanBypass scanSELECTED DATAREGISTERBoundary scanBypassBoundary scanBoundary scanBypassBypassBypassBypassBypassBypassBoundary scanBoundary scanBoundary scanBypassBoundary controlBoundary controlBypassMODETestNormalNormalTestNormalNormalModified testTestNormalTestNormalTestNormalTestNormalTestNormal†Bit 7 is used to maintain even parity in the 8-bit instruction.‡The BYPASS instruction is executed in lieu of a SCOPE™ instruction that is not supported in the ’ABT8543.boundary scanThis instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR isselected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while dataappearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scannedinto the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned intothe output BSCs is applied to the device output pins. The device operates in the test mode.bypass scanThis instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register isselected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The deviceoperates in the normal mode.sample boundaryThis instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR isselected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while dataappearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in thenormal mode.10POST OFFICE BOX 655303 DALLAS, TEXAS 75265•http://oneic.com/
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SN74ABT8543DWSN74ABT8543DLRG4SN74ABT8543DLG4SN74ABT8543DWRG4
SN74ABT8543DLSN74ABT8543DWE4SN74ABT8543DWR
SN74ABT8543DLRSN74ABT8543DWG4SN74ABT8543DWRE4
