ics952801

Systems, Inc.

ICS952801

Advance Information

Programmable Timing Control Hub™ for K8™ processor

Recommended Application:

SiS755/760 style chipset for AMD K8 ProcessorOutput Features:•2 - Pairs of differential push-pull K8CPU outputs•8 - PCICLK @ 3.3V•2 - AGPCLK @ 3.3V•3 - REF @ 3.3V•2 - ZCLK @ 3.3V•1 - 24_48MHz @ 3.3V•1 - 48MHz @ 3.3VKey Specifications:•CPU Output Jitter <250ps•AGP Output Jitter <250ps•ZCLK Output Jitter <250ps•PCI Output Jitter <500psFunctionality

Bit4FS400000000000000001111111111111111Bit3FS300000000111111110000000011111111Bit2FS200001111000011110000111100001111Bit1FS100110011001100110011001100110011Bit0FS001010101010101010101010101010101CPUMHz200.00200.00200.00200.00233.33233.33233.33233.33266.67266.67266.67266.67293.34293.34293.34293.34133.33133.33133.33133.33166.67166.67166.67166.67202.00202.00202.00202.00220.00220.00220.00220.00ZCLKMHz66.67100.00133.33166.6766.6793.33133.33175.0066.67106.67133.33160.0073.34117.34146.66176.0066.67100.00133.33166.6766.67100.00133.33166.6767.34101.00134.66168.3473.34110.00146.66183.34AGPMHz66.6766.6766.6766.6766.6766.6766.6770.0066.6766.6766.6766.6773.3373.3373.3373.3366.6766.6766.6766.6766.6766.6766.6766.6767.3367.3367.3367.3373.3373.3373.3373.33PCIMHz33.3333.3333.3333.3333.3333.3333.3335.0033.3333.3333.3333.3336.6636.6636.6636.6633.3333.3333.3333.3333.3333.3333.3333.3333.6633.6633.6633.6636.6636.6636.6636.66Features/Benefits:•QuadRomTM frequency selection.•Selectable synchronous/asynchronous AGP/PCI/ZCLK

frequency•Linear Programmable CPU output frequency.•Linear Programmable AGP/PCI output frequency.•Programmable output divider ratios.•Programmable output rise/fall time.•Programmable output skew.•Programmable spread percentage for EMI control.•Watchdog timer technology to reset system if system

malfunctions.•Programmable watch dog safe frequency.•Support I2C Index read/write and block read/write

operations.•Uses external 14.318MHz referience input.Pin Configuration

VDDREF1**FS0/REF02**FS1/REF13**FS2/REF24GNDREF5

X16X27GNDZ8ZCLK09VDDZ11

*PCI_STOP#12**FS3/PCICLK_F013**FS4/PCICLK_F114

VDDPCI15GNDPCI16PCICLK017PCICLK118PCICLK219PCICLK320PCICLK421PCICLK522GNDPCI23VDDPCI24ZCLK110

48CPU_STOP#*47GNDCPU46CPUCLK8T145CPUCLK8C1

44VDDCPU43VDDCPU42CPUCLK8T041CPUCLK8C040GNDCPU

ICS95280139AGND38AVDD37PD#*

36GNDAGP35AGPCLK034AGPCLK133VDDAGP32SCLK31AVDD483048MHz

2924_48MHz/SEL24_48MHz*28GND4827SDATA26PCICLK725PCICLK6

48-SSOP

* Internal Pull-Up Resistor** Internal Pull-Down Resistor

0719—01/22/03

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

General Description

The ICS952801 is a two chip clock solution for desktop designs using SIS 755/760 style chipsets. When used with a zerodelay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clockssignals for such a system.

The ICS952801 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is thefirst to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing theuse of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, theoutput divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling eachindividual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe settingunder unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.

Block Diagram

PLL2X1X2FrequencyDividers48MHz24_48MHzXTALREF (2:0)CPUCLK8T (1:0)CPUCLK8C (1:0)ProgrammableSpreadPLL1ControlLogicProgrammableFrequencyDividersSTOPLogicAGPCLK (1:0)PCICLK (5:0)PCICLKF (1:0)ZCLK (1:0)PD#CPU_STOP#PCI_STOP#FS (4:0)SEL24_48MHZPower Groups

Pin NumberVDD13138GND52836DescriptionREF Output, Crystal24/48MHz, Fix Analog, Fix DigitalCPU PLL, CPU Analog, MCLK0719—01/22/03

2

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Pin Description

PIN#12345671011VDDREF**FS0/REF0**FS1/REF1**FS2/REF2GNDREFX1X2GNDZZCLK0ZCLK1VDDZPINNAMEPINTYPEDESCRIPTIONPWRRef, XTAL power supply, nominal 3.3VI/OI/OI/OPWRINOUTPWROUTOUTPWRFrequency select latch input pin / 14.318 MHz reference clock.Frequency select latch input pin / 14.318 MHz reference clock.Frequency select latch input pin / 14.318 MHz reference clock.Ground pin for the REF outputs.Crystal input,nominally 14.318MHz. Crystal output, Nominally 14.318MHzGround pin for the ZCLK outputs3.3V Hyperzip clock output.3.3V Hyperzip clock output.Power supply for ZCLK clocks, nominal 3.3VPCI clock output, this output is activated by the Mode selection pin / Stops all PCICLKs 12I/O*PCI_STOP#besides the PCICLK_F clocks at logic 0 level, when input low. 13**FS3/PCICLK_F0I/OFrequency select latch input pin / 3.3V PCI free running clock output.14**FS4/PCICLK_F1I/OFrequency select latch input pin / 3.3V PCI free running clock output.15VDDPCIPWRPower supply for PCI clocks, nominal 3.3V16GNDPCIPWRGround pin for the PCI outputs17PCICLK0OUTPCI clock output. 18PCICLK1OUTPCI clock output. 19PCICLK2OUTPCI clock output. 20PCICLK3OUTPCI clock output. 21PCICLK4OUTPCI clock output. 22PCICLK5OUTPCI clock output. 23GNDPCIPWRGround pin for the PCI outputs24VDDPCIPWRPower supply for PCI clocks, nominal 3.3V25PCICLK6OUTPCI clock output. 26PCICLK7OUTPCI clock output. 27SDATAI/OData pin for I2C circuitry 5V tolerant 28GND48PWRGround pin for the 48MHz outputs24/48MHz clock output / Latched select input for 24/48MHz output. 0=24mHz, 1 = 2924_48MHz/SEL24_48MHz*I/O48MHz.3048MHzOUT48MHz clock output.31AVDD48PWRPower for 24/48MHz outputs and fixed PLL core, nominal 3.3V32SCLKINClock pin of I2C circuitry 5V tolerant 33VDDAGPPWRPower supply for AGP clocks, nominal 3.3V34AGPCLK1OUTAGP clock output35AGPCLK0OUTAGP clock output36GNDAGPPWRGround pin for the AGP outputsAsynchronous active low input pin used to power down the device into a low power 37PD#*INstate. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms.38AVDDPWR3.3V Analog Power pin for Core PLL39AGNDPWRAnalog Ground pin for Core PLL40GNDCPUPWRGround pin for the CPU outputs41CPUCLK8C0OUT\"Complementary\" clocks of differential 3.3V push-pull K8 pair.42CPUCLK8T0OUT\"True\" clocks of differential 3.3V push-pull K8 pair.43VDDCPUPWRSupply for CPU clocks, 3.3V nominal44VDDCPUPWRSupply for CPU clocks, 3.3V nominal45CPUCLK8C1OUT\"Complementary\" clocks of differential 3.3V push-pull K8 pair.46CPUCLK8T1OUT\"True\" clocks of differential 3.3V push-pull K8 pair.47GNDCPUPWRGround pin for the CPU outputs48CPU_STOP#*INStops all CPUCLK besides the free running clocks * Internal Pull-Up Resistor** Internal Pull-Down Resistor0719—01/22/03

3

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

General I2C serial interface information for the ICS952801

How to Write:

••••••••

Controller (host) sends a start bit.

Controller (host) sends the write address D2 (H)ICS clock will acknowledgeController (host) sends the begining byte location = NICS clock will acknowledgeController (host) sends the data byte count = XICS clock will acknowledgeController (host) starts sending Byte N throughByte N + X -1(see Note 2)

•ICS clock will acknowledge each byte one at a time•Controller (host) sends a Stop bit

How to Read:

••••••••••••••

Controller (host) will send start bit.

Controller (host) sends the write address D2 (H)ICS clock will acknowledgeController (host) sends the begining bytelocation = N

ICS clock will acknowledgeController (host) will send a separate start bit.Controller (host) sends the read address D3 (H)ICS clock will acknowledgeICS clock will send the data byte count = XICS clock sends Byte N + X -1ICS clock sends Byte 0 through byte X (if X(H)was written to byte 8).

Controller (host) will need to acknowledge eachbyte

Controllor (host) will send a not acknowledge bitController (host) will send a stop bit

Index Block Write OperationController (Host)starT bitT Slave Address D2(H)WRWRiteBeginning Byte = NACKData Byte Count = XACKBeginning Byte NACKX ByteICS (Slave/Receiver)Index Block Read OperationController (Host)TstarT bit Slave Address D2(H)WRWRiteBeginning Byte = NACKRTRepeat starT Slave Address D3(H)RDReaDACKData Byte Count = XACK Beginning Byte NICS (Slave/Receiver)ACKACKByte N + X - 1ACKPstoP bitACKX ByteByte N + X - 1NPNot acknowledgestoPbit0719—01/22/03

4

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Table1: QuadRom Frequency Selection TableBit6Bit5Bit4Bit3Bit2Bit1Bit0XXFS4FS3FS2FS1FS000000000000001000001000000110000100000010100001100000111000100000010010001010000101100011000001101000111000011110010000001000100100100010011001010000101010010110001011100110000011001001101000110110011100001110100111100011111CPUMHz200.00200.00200.00200.00233.33233.33233.33233.33266.67266.67266.67266.67293.34293.34293.34293.34133.33133.33133.33133.33166.67166.67166.67166.67202.00202.00202.00202.00220.00220.00220.00220.00ZCLKMHz66.67100.00133.33166.6766.6793.33133.33175.0066.67106.67133.33160.0073.34117.34146.66176.0066.67100.00133.33166.6766.67100.00133.33166.6767.34101.00134.66168.3473.34110.00146.66183.34AGPMHz66.6766.6766.6766.6766.6766.6766.6770.0066.6766.6766.6766.6773.3373.3373.3373.3366.6766.6766.6766.6766.6766.6766.6766.6767.3367.3367.3367.3373.3373.3373.3373.33PCIMHz33.3333.3333.3333.3333.3333.3333.3335.0033.3333.3333.3333.3336.6636.6636.6636.6633.3333.3333.3333.3333.3333.3333.3333.3333.6633.6633.6633.6636.6636.6636.6636.66Spread%0.3% Center0.3% Center0.3% Center0.3% Center0.3% Center0.3% Center0.3% Center0.3% CenterSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread Off0.3% Center0.3% Center0.3% Center0.3% Center0.3% Center0.3% Center0.3% Center0.3% CenterB24b2:1 =11B24b2:1 =11B24b2:1 =11B24b2:1 =11Spread OffSpread OffSpread OffSpread Off0719—01/22/03

5

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Table1: QuadRom Frequency Selection Table ContinuedBit6Bit5Bit4Bit3Bit2Bit1Bit0CPUXXFS4FS3FS2FS1FS0MHz0100000206.000100001206.000100010206.000100011206.000100100240.330100101240.330100110240.330100111240.330101000274.670101001274.670101010274.670101011274.670101100302.140101101302.140101110302.140101111302.140110000137.330110001137.330110010137.330110011137.330110100171.670110101171.670110110171.670110111171.670111000208.060111001208.060111010208.060111011208.060111100226.600111101226.600111110226.600111111226.60ZCLKMHz68.67103.00137.33171.6768.6796.13137.33180.2568.67109.87137.331.8075.54120.86151.06181.2868.67103.00137.33171.6768.67103.00137.33171.6769.36104.03138.70173.3975.54113.30151.06188.84AGPMHz68.6768.6768.6768.6768.6768.6768.6772.1068.6768.6768.6768.6775.5375.5375.5375.5368.6768.6768.6768.6768.6768.6768.6768.6769.3569.3569.3569.3575.5375.5375.5375.53PCIMHz34.3334.3334.3334.3334.3334.3334.3336.0534.3334.3334.3334.3337.7637.7637.7637.7634.3334.3334.3334.3334.3334.3334.3334.3334.6734.6734.6734.6737.7637.7637.7637.76Spread%Spread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread Off0719—01/22/03

6

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Table1: QuadRom Frequency Selection Table ContinuedBit6Bit5Bit4Bit3Bit2Bit1Bit0CPUXXFS4FS3FS2FS1FS0MHz1000000214.001000001214.001000010214.001000011214.001000100249.661000101249.661000110249.661000111249.661001000285.341001001285.341001010285.341001011285.341001100313.871001101313.871001110313.871001111313.871010000142.661010001142.661010010142.661010011142.661010100178.341010101178.341010110178.341010111178.341011000216.141011001216.141011010216.141011011216.141011100235.401011101235.401011110235.401011111235.40ZCLKMHz71.34107.00142.66178.3471.3399.86142.66187.2571.34114.14142.66171.2078.47125.55156.93188.3271.34107.00142.66178.3471.34107.00142.66178.3472.05108.07144.09180.1278.47117.70156.93196.17AGPMHz71.3371.3371.3371.3371.3371.3371.3374.9071.3371.3371.3371.3378.4778.4778.4778.4771.3371.3371.3371.3371.3371.3371.3371.3372.0572.0572.0572.0578.4778.4778.4778.47PCIMHz35.6635.6635.6635.6635.6635.6635.6637.4535.6635.6635.6635.6639.2339.2339.2339.2335.6635.6635.6635.6635.6635.6635.6635.6636.0236.0236.0236.0239.2339.2339.2339.23Spread%Spread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread Off0719—01/22/03

7

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Table1: QuadRom Frequency Selection Table ContinuedBit6Bit5Bit4Bit3Bit2Bit1Bit0CPUXXFS4FS3FS2FS1FS0MHz1100000220.001100001220.001100010220.001100011220.001100100256.661100101256.661100110256.661100111256.661101000293.341101001293.341101010293.341101011293.341101100322.671101101322.671101110322.671101111322.671110000146.661110001146.661110010146.661110011146.661110100183.341110101183.341110110183.341110111183.341111000222.201111001222.201111010222.201111011222.201111100242.001111101242.001111110242.001111111242.00ZCLKMHz73.34110.00146.66183.3473.33102.66146.66192.5073.34117.34146.66176.0080.67129.07161.33193.6073.34110.00146.66183.3473.34110.00146.66183.3474.07111.10148.13185.1780.67121.00161.33201.67AGPMHz73.3373.3373.3373.3373.3373.3373.3377.0073.3373.3373.3373.3380.6780.6780.6780.6773.3373.3373.3373.3373.3373.3373.3373.3374.0774.0774.0774.0780.6780.6780.6780.67PCIMHz36.6636.6636.6636.6636.6636.6636.6638.5036.6636.6636.6636.60.3340.3340.3340.3336.6636.6636.6636.6636.6636.6636.6636.6637.0337.0337.0337.0340.3340.3340.3340.33Spread%Spread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread OffSpread Off0719—01/22/03

8

IntegratedCircuit

Systems, Inc.

IC Table: Function Control RegisterByte 0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0-26-25----Pin #NamePDENPCICLK7WDS_ENPCICLK6AFS1AFS0AEN1AEN0Control FunctionPD# EnableOutput ControlWD Soft EnableOutput ControlAsync Rom SEL_1Async Rom SEL_0Zclk/Agp/Pci Freq Source Select ControlTypeRWRWRWRWRWRWRWRW2

ICS952801

Advance Information

01PWD11110000DisableEnableDisableEnableDisableEnableDisableEnableSee Table 3: Async Z-CLK Frequency Selection TableSee Table 4 : ZCLK, AGP & PCI Frequency Source Decode TableTable 3: Asynchronous ZCLK Frequency Selection TableByte0 Bit30011Byte0 Bit20101ZCLK Frequency.0172.0182.30144.02Table 4: ZCLK, AGP & PCI Frequency Source Decode TableByte0 Bit10011Byte0 Bit00101ZCLK & AGP & PCISee Table 1, QuadRom Frequency TableN-Programming for AGP/PCI/ZCLKSee Table 1 for AGP/PCI, Table 3 for ZCLKN-Programming for AGP/PCI, Table 3 for ZCLKIC Table: Async N-Programming Frequency Select RegisterByte 1Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 02

2

Pin #--------NameN PLL3 Div7N PLL3 Div6N PLL3 Div5N PLL3 Div4N PLL3 Div3N PLL3 Div2N PLL3 Div1N PLL3 Div0Control FunctionThe decimal representation of N PLL2 Div (7:0) + 8 is equal to VCO divider value for PLL2. Default at power up = 66.67MHzTypeRWRWRWRWRWRWRWRW0--------1--------PWD01000111IC Table: Reserved RegisterByte 2Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0-------Pin #NameReservedReservedReservedReservedReservedReservedReservedReservedControl FunctionReservedReservedReservedReservedReservedReservedReservedReservedTypeRWRWRWRWRWRWRWRW0--------1--------PWD111111110719—01/22/03

9

IntegratedCircuit

Systems, Inc.

IC Table: Reserved RegisterByte 3Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 022

ICS952801

Advance Information

Pin #-------NameReservedReservedReservedReservedReservedReservedReservedReservedControl FunctionReservedReservedReservedReservedReservedReservedReservedReservedTypeRWRWRWRWRWRWRWRW0--------1--------PWD11111111IC Table: Frequency Select RegisterByte 4Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameFS3FS2FS1FS0FS SourceFS4SS_ENOutputsControl FunctionFreq Select Bit 7Freq Select Bit 6Freq Select Bit 5Freq Select Bit 4Frequency HW/IIC SelectFreq Select Bit 2Spread EnableOutput ControlTypeRWRWRWRWRWRWRWRW01PWD00000010See Table1 : Quad Rom Frequency Selection TableLatch InputIICSee Table1OFFONRunningTri-stateIC Table: Read Back RegisterByte 5Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameWDHRBWDSRBMULTISELFS4RBFS3RBFS2RBFS1RBFS0RBControl FunctionWD Hard Alarm Status Read backWD Soft Alarm Status Read backMultisel Read backFS4 Read backFS3 Read backFS2 Read backFS1 Read backFS0 Read backTypeRRRRRRRR0NormalNormal------1AlarmAlarm------PWDXXXXXXXX2

IC Table: Output Control RegisterByte 6Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 00719—01/22/03

2

Pin #109131442, 4146, 4542, 4146, 45NameZCLK_1ZCLK_0PCICLK_F0PCICLK_F1CPUCLK8T0/C0CPUCLK8T1/C1CPUCLK8T0/C0CPUCLK8T1/C1Control FunctionOutput ControlOutput ControlPCI_STOP# ControlPCI_STOP# ControlCPU_STOP# ControlCPU_STOP# ControlOutput ControlOutput ControlTypeRWRWRWRWRWRWRWRW01PWD11001111DisableEnableDisableEnableStop DisableStop EnableStop DisableStop EnableStop DisableStop EnableStop DisableStop EnableDisableEnableDisableEnable10

IntegratedCircuit

Systems, Inc.

IC Table: Output Control RegisterByte 7Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 01413222120191817Pin #NamePCICLK_F1PCICLK_F0PCICLK5PCICLK4PCICLK3PCICLK2PCICLK1PCICLK0Control FunctionOutput ControlOutput ControlOutput ControlOutput ControlOutput ControlOutput ControlOutput ControlOutput ControlTypeRWRWRWRWRWRWRWRW2

ICS952801

Advance Information

0DisableDisableDisableDisableDisableDisableDisableDisable1EnableEnableEnableEnableEnableEnableEnableEnablePWD11111111IC Table: Byte Count RegisterByte 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameBC7BC6BC5BC4BC3BC2BC1BC0Control FunctionWriting to this register will configure how many bytes will be read back, default is 0F = 15 bytes.TypeRWRWRWRWRWRWRWRW0--------1--------PWD000011112

IC Table: Watchdog Timer RegisterByte 9Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameWD7WD6WD5WD4WD3WD2WD1WD0Control FunctionThese bits represent X*290ms the watchdog timer will wait before it goes to alarm mode. Default is 16 X 290ms =4. secondsTypeRWRWRWRWRWRWRWRW0--------1--------PWD000100002

IC Table: VCO Control Select Bit & WD Timer Control RegisterByte 10Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 00719—01/22/03

2

Pin #--------NameM/NENWDENReservedWD SF4WD SF3WD SF2WD SF1WD SF0Control FunctionM/N Programming EnableWatchdog EnableReservedWriting to these bit will configure the safe frequency as Byte4bit 2, (7:4), Byte 24bit(6:5)TypeRWRRWRWRWRWRWRW0DisableDisable------1EnableEnable------PWD0000000111

IntegratedCircuit

Systems, Inc.

IC Table: VCO Frequency Control Register Byte 11Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameN Div8M Div6M Div5M Div4M Div3M Div2M Div1M Div0Control FunctionN Divider Bit 8The decimal representation of M Div (6:0) + 2 is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table.TypeRWRWRWRWRWRWRWRW2

ICS952801

Advance Information

0--------1--------PWDXXXXXXXXIC Table: VCO Frequency Control Register Byte 12Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameN Div7N Div6N Div5N Div4N Div3N Div2N Div1N Div0Control FunctionThe decimal representation of N Div (8:0) + 8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table.TypeRWRWRWRWRWRWRWRW0--------1--------PWDXXXXXXXX2

IC Table: Spread Spectrum Control RegisterByte 13Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameSSP7SSP6SSP5SSP4SSP3SSP2SSP1SSP0Control FunctionThese Spread Spectrum bits will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming.TypeRWRWRWRWRWRWRWRW0--------1--------PWDXXXXXXXX2

IC Table: Spread Spectrum Control RegisterByte 14Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 00719—01/22/03

2

Pin #--------NameReservedReservedSSP13SSP12SSP11SSP10SSP9SSP8Control FunctionReservedReservedIt is recommended to use ICS Spread % table for spread programming.TypeRRRWRWRWRWRWRW0--------1--------PWD00XXXXXX12

IntegratedCircuit

Systems, Inc.

IC Table: Output Divider Control RegisterByte 15Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameReservedReservedReservedReservedCPU Div3CPU Div2CPU Div1CPU Div0Control FunctionReservedReservedReservedReservedCPU divider ratio can be configured via these 4 bits individually.TypeRWRWRWRWRWRWRWRW2

ICS952801

Advance Information

0----1----PWDXXXXXXXXSee Table 5: Divider Ratio Combination TableTable 5: CPU Divider Ratio Combination TableDivider (3:2)Bit00Divider (1:0)011011LSB2

0010000000100100011Address2357Div0120100010101100111Address461014Div1041000100110101011Address8122028Div111100110111101111AddressMSB816244056DivIC Table: Output Divider Control RegisterByte 16Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameReservedReservedReservedReservedReservedReservedReservedReservedControl FunctionReservedReservedReservedReservedReservedReservedReservedReservedTypeRWRWRWRWRWRWRWRW0--------1--------PWDXXXXXXXXIC Table: Output Divider Control RegisterByte 17Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 00719—01/22/03

2

Pin #--------NameReservedReservedReservedCPUINVReservedReservedReservedReservedControl FunctionReservedReservedReservedCPU Phase InvertReservedReservedReservedReservedTypeRWRWRWRWRWRWRWRW0---Default----1---Inverse----PWDXXXXXXXX13

IntegratedCircuit

Systems, Inc.

IC Table: Group Skew Control RegisterByte 18Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameReservedReservedReservedReservedReservedReservedReservedReservedControl FunctionReservedReservedReservedReservedReservedReservedReservedReservedTypeRWRWRWRWRWRWRWRW2

ICS952801

Advance Information

0--------1--------PWDXXXXXXXXIC Table: Group Skew Control RegisterByte 19Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NameZCLKSkw1ZCLKSkw0ReservedReservedAGPSkw1AGPSkw0ReservedReservedControl FunctionCPU-ZCLK Skew ControlReservedReservedCPU-AGP Skew ControlReservedReservedTypeRWRWRWRWRWRWRWRW01PWD000000002

See Table 6: 4-Steps Skew Programming Table----See Table 6: 4-Steps Skew Programming Table----IC Table: Group Skew Control RegisterByte 20Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #NamePCI_FSkw1PCI_FSkw0ReservedReservedPCISkw1PCISkw0ReservedReservedControl FunctionCPU-PCI_F Skew ControlReservedReservedCPU-PCI Skew ControlReservedReservedTypeRWRWRWRWRWRWRWRW01PWD000000002

See Table 6: 4-Steps Skew Programming Table----See Table 6: 4-Steps Skew Programming Table----Table 6: 4-Steps Skew Programming Table4 Step01MSB00ps500ps-1250ps750ps-LSB---0719—01/22/03

14

IntegratedCircuit

Systems, Inc.

IC Table: Slew Rate Control RegisterByte 21Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--------Pin #Name24/48Slw124/48Slw0AGPSlw1AGPSlw0ZCLKSlw1ZCLKSlw0REFSlw1REFSlw0Control Function24/48 Slew Rate ControlAGP Slew Rate ControlZCLK Slew Rate ControlREF Slew Rate ControlTypeRWRWRWRWRWRWRWRW2

ICS952801

Advance Information

0--------1--------PWD00000000IC Table: Slew Rate Control RegisterByte 22Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0--3435----Pin #NameSDSlw1SDSlw0AGPCLK1AGPCLK0PCI_FSlw1PCI_FSlw0PCISlw1PCISlw0Control FunctionSD Slew Rate ControlOutput ControlOutput ControlPCI_F Slew Rate ControlPCI Slew Rate ControlTypeRWRWRWRWRWRWRWRW0--DisableDisable----1--EnableEnable----PWD001100002

IC Table: Output Control RegisterByte 23Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0---3029432Pin #NameReservedSEL24_48Reserved48MHz24_48MHzREF2REF1REF0Control FunctionReserved24MHz or 48MHz ReservedOutput ControlOutput ControlOutput ControlOutput ControlOutput ControlTypeRWRWRWRWRWRWRWRW0-48MHz-Disable Disable Disable Disable Disable 1-24MHz-EnableEnableEnableEnableEnablePWD011111112

IC Table: Reserved RegisterByte 24Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0-------Pin #NameReservedFS6FS5ReservedReservedSS_SELSS_SELReservedControl FunctionReservedFreq Select bit 6Freq Select bit 5ReservedReservedSS Scheme Select1SS Scheme Select1ReservedTypeRWRWRWRWRWRWRWRW0-See Table 1----See Table 2: Spread Spectrum Selection Table--1-PWD000000002

0719—01/22/03

15

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Table2: Spread Spectrum Select TableSS1(Byte 24 bit 2)0011SS0(Byte 24 bit 1)0101For Spreadable Frequency Only0.35%0.50%0.75%2.50%0719—01/22/03

16

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Absolute Maximum Ratings

Core Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature. . . . . . . . . . . . . Storage Temperature. . . . . . . . . . . . . . . . . . . . . . Case Temperature. . . . . . . . . . . . . . . . . . . . . . . .

4.6 V3.6V

GND –0.5 V to VDD +0.5 V0°C to +70°C–65°C to +150°C115°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stressspecifications only and functional operation of the device at these or any other conditions above those listed in the operationalsections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect productreliability.

Electrical Characteristics - Input/Supply/Common Output ParametersTA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)PARAMETERSYMBOLCONDITIONSMIN2Input High VoltageVIHVSS - 0.3Input Low VoltageVILVIN = VDDInput High CurrentIIHVIN = 0 V; Inputs with no pull-up resistors-5Input Low CurrentIIL1VIN = 0 V; Inputs with pull-up resistors-200Input Low CurrentIIL2Operating Supply IDD(op)CL = 0 pF; Select @ 100MHzCurrentCL = 0 pF; With input address to Vdd or Power Down Supply IDDPDCurrentGNDInput frequencyFiVDD = 3.3 V;11Logic InputsCINInput Capacitance1X1 & X2 pins27CINXTtransTo 1st crossing of target Freq.Transition Time1TSTABFrom VDD = 3.3 V to 1% target Freq.Clk Stabilization1TCPU-PCIVT = 1.5 V1.5Skew11TYPMAXUNITSVDD + 0.3V0.8V5mAmAmA1804016545334mAmAMHzpFpFmsmsnsGuaranteed by design, not 100% tested in production.0719—01/22/03

17

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Electrical Characteristics - ZCLK

TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)PARAMETEROutput FrequencyOutput ImpedanceOutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentRise TimeFall TimeDuty CycleSYMBOLFO1RDSP11VOH1VOL1IOH1IOL1tr11tf11IOH = -1 mAIOL = 1 mAV OH@MIN = 1.0 V, V OH@MAX = 3.135 VVOL @MIN = 1.95 V, VOL @MAX = 0.4 VVOL = 0.4 V, VOH = 2.4 VVOH = 2.4 V, VOL = 0.4 VVT = 1.5 VVT = 1.5 V VT = 1.5 V 3V66 CONDITIONSVO = VDD*(0.5)MIN122.4-33300.50.5450.55-33382255250250TYPMAXUNITSMHz55ΩVVmAmAnsns%pspsdt11Skew tsk11tjcyc-cyc1JitterElectrical Characteristics - AGPCLK, ZCLKTA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)PARAMETEROutput FrequencyOutput ImpedanceOutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentRise TimeFall TimeDuty CycleSYMBOLFO1RDSP11VOH1VOL1CONDITIONSVO = VDD*(0.5)IOH = -1 mAIOL = 1 mAV OH@MIN = 1.0 V, V OH@MAX = 3.135 VVOL @MIN = 1.95 V, VOL @MAX = 0.4 VVOL = 0.4 V, VOH = 2.4 VVOH = 2.4 V, VOL = 0.4 VVT = 1.5 VVT = 1.5 V VT = 1.5 V 3V66 MIN122.4-33300.50.545TYPMAXUNITSMHz550.55-33382255250250ΩVVmAmAnsns%pspsIOH1IOL1tr11tf11dt11Skew tsk11tjcyc-cyc1JitterElectrical Characteristics - PCICLKTA = 0 - 70C; VDD = 3.3 V,+/-5%; CL = 30 pFPARAMETEROutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentRise Time1Fall Time1Duty CycleSkew11SYMBOLVOH1VOL1IOH1IOL1tr1tf1dt1tsk1tjcyc-cyc1tjabs1CONDITIONSIOH = -18 mAIOL = 9.4 mAVOH = 2.0 VVOL = 0.8 VVOL = 0.4 V, VOH = 2.4 VVOH = 2.4 V, VOL = 0.4 VVT = 1.5 VVT = 1.5 VVT = 1.5 VVT = 1.5 VMIN2.1TYP16MAXUNITSV0.4V-22mA57mA22nsns%pspsps4555500500500Jitter1Guaranteed by design, not 100% tested in production.

0719—01/22/03

18

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Electrical Characteristics - 48MHz, 24_48MHz

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)PARAMETERSYMBOLCONDITIONS1Output ImpedanceVO = VDD*(0.5)RDSP1Output High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentRise TimeFall TimeDuty CycleJitter1MIN202.4TYPMAX600.4UNITSΩVVmAmAnsns%psVOH1VOL1IOH1IOL1tr11tf11dt11tjcyc-cyc1IOH = -1 mAIOL = 1 mAV OH@MIN = 1.0 V V OH@MAX = 3.135 VVOL @MIN = 1.95 VVOL @MAX = 0.4 VVOL = 0.4 V, VOH = 2.4 VVOH = 2.4 V, VOL = 0.4 VVT = 1.5 VVT = 1.5 V-29-23290.50.545271155350Guaranteed by design, not 100% tested in production.Electrical Characteristics - REFTA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)PARAMETEROutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentRise Time1Fall Time1SYMBOLVOH5VOL5IOH5IOL5tr5tf5dt5tjcyc-cyc5tjabs5CONDITIONSIOH = -12 mAIOL = 9 mAVOH = 2.0 VVOL = 0.8 VVOL = 0.4 V, VOH = 2.4 VVOH = 2.4 V, VOL = 0.4 VVT = 1.5 VVT = 1.5 VVT = 1.5 VMIN2.6TYP16MAXUNITSV0.4V-22mAmA44nsns%pspsDuty Cycle1Jitter1455510008000719—01/22/03

19

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Electrical Characteristics - CPUCLK

TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)PARAMETEROutput ImpedanceOutput High VoltageOutput Low VoltageOutput Low CurrentRise Edge Rate1Fall Edge Rate1VDIFFSYMBOLZOVOH2BVOL2BIOL2BCONDITIONSVO = VXMIN15118220.4772.3TYPMAX551.20.4UNITSWVVmAV/nsV/nsVVOL = 0.3 VMeasured from 20-80%Measured from 80-20%Differential Voltage, Measured @ the Hammer test load (single-ended measurement)Change in VDIFF_DC magnitude, Measured @ the Hammer test load (single-ended measurement)Common Mode Voltage, Measured @ the Hammer test load (single-ended measurement)Change in Common Mode Voltage, Measured @ the Hammer test load (single-ended measurement)DVDIFF-150150mVVCM1.051.45VDVCM-200200mVdt2BVT = 50%4553%Duty Cycle1tjcyc-cyc2BVT = VX0200psJitter, Cycle-to-cycle1Notes:

1 - Guaranteed by design, not 100% tested in production.

2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the \"true\" input level and VCP is the \"complement\" input level.

3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV

0719—01/22/03

20

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

Shared Pin Operation -Input/Output Pins

The I/O pins designated by (input/output) serve as dualsignal functions to the device. During initial power-up, theyact as input pins. The logic level (voltage) that is present onthese pins at this time is read and stored into a 5-bit internaldata latch. At the end of Power-On reset, (see ACcharacteristics for timing values), the device changes themode of operations for these pins to an output function. Inthis mode the pins produce the specified buffered clocks toexternal loads.

To program (load) the internal configuration register for thesepins, a resistor is connected to either the VDD (logic 1) powersupply or the GND (logic 0) voltage potential. A 10 Kilohm (10K)resistor is used to provide both the solid CMOS programmingvoltage needed during the power-up programming period and toprovide an insignificant load on the output clock during thesubsequent operating period.

Figure 1 shows a means of implementing this functionwhen a switch or 2 pin header is used. With no jumper isinstalled the pin will be pulled high. With the jumper inplace the pin will be pulled low. If programmability is notnecessary, than only a single resistor is necessary. Theprogramming resistors should be located close to the seriestermination resistor to minimize the current loop area. It ismore important to locate the series termination resistorclose to the driver than the programming resistor.

ProgrammingHeaderVia to GndDevicePadSeriesTerm.Res.2KVia toVDD8.2KClock trace to loadFig. 1

0719—01/22/03

21

IntegratedCircuit

Systems, Inc.

ICS952801

Advance Information

NcSYMBOLLE1INDEXAREAE1 2h x 45°DαAA1AA1bcDEE1ehLNαIn MillimetersCOMMON DIMENSIONSMINMAX2.412.800.200.400.200.340.130.25SEE VARIATIONS10.0310.687.407.600.635 BASIC0.380.0.501.02SEE VARIATIONS0°8°VARIATIONSD mm.MINMAX15.7516.00In InchesCOMMON DIMENSIONSMINMAX.095.110.008.016.008.0135.005.010SEE VARIATIONS.395.420.291.2990.025 BASIC.015.025.020.040SEE VARIATIONS0°8°- C -ebSEATINGPLANE.10(.004)CN4810-0034

D (inch)MIN.620MAX.630Reference Doc.: JEDEC Publication 95, MO-118

Ordering Information

ICS952801yFTExample:

ICS XXXXX y F - TDesignation for tape and reel packagingPackage Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)Device Type

Prefix

ICS = Standard Device

0719—01/22/03

22