LR36B15
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2. When using this product, please observe the absolute maximum ratings and the instructions for use outlined in these specification sheets, as well as the precautions mentioned below.
Sharp assumes no responsibility for any damage resulting from use of the product which does not comply with the absolute maximum ratings and the instructions included in these specification sheets, and the precautions mentioned below.
(Precautions)
(1) Please do verify the validity of this part after assembling it in customer’s products, when customer wants to make catalogue and instruction manual based on the specification sheet of this part.
(2) This product is designed for use in the following application areas ; · OA equipment Audio visual equipment · Home appliances
· Telecommunication equipment (Terminal) · Measuring equipment · Tooling machines · Computers
If the use of the product in the above application areas is for equipment listed in paragraphs (3) or (4), please be sure to observe the precautions given in those respective paragraphs.
(3) Appropriate measures, such as fail-safe design and redundant design considering
the safety design of the overall system and equipment, should be taken to ensure reliability and safety when this product is used for equipment which demands high reliability and safety in function and precision, such as ;
· Transportation control and safety equipment (aircraft, train, automobile etc.) · Traffic signals · Gas leakage sensor breakers · Rescue and security equipment · Other safety equipment (4) Please do not use this product for equipment which require extremely high reliability and safety in function and precision, such as ;
· Space equipment · Telecommunication equipment (for trunk lines) · Nuclear power control equipment · Medical equipment (5) Please contact and consult with a Sharp sales representative if four are any questions regarding interpretation of the above four paragraphs. 3. Please contact and consult with a Sharp sales representative for any questions about this product.
LR36B15 1
Table of contents
1. Description ........................................................................................................................................ 2 2. Pin Assignment .................................................................................................................................. 3 3. Pin Description .................................................................................................................................. 4 4. Block Diagram ................................................................................................................................... 8 5. Electrical characteristics .................................................................................................................. 10 5.1. Absolute maximum ratings.......................................................................................................... 10 5.2. Recommended operating conditions ............................................................................................. 11 5.3. DC characteristics ...................................................................................................................... 12 5.4. Analog characteristics ................................................................................................................. 13 5.4.1. AFE block ............................................................................................................................ 13 5.4.2. Analog output block .............................................................................................................. 15 5.4.3. Crystal oscillator ................................................................................................................... 16 5.4.4. Regulator block ..................................................................................................................... 17 5.5. AC timing ................................................................................................................................. 18 5.5.1. 2-wired serial system bus I/O timing........................................................................................ 18 5.5.2. Reset pulse ........................................................................................................................... 20 5.5.3. Power ON/OFF sequences...................................................................................................... 20 6. System Architecture......................................................................................................................... 21 6.1. CCD Sensor............................................................................................................................... 21 6.2. Host I/F ..................................................................................................................................... 21 6.3. EEPROM .................................................................................................................................. 21 6.4. Host I/F access by 2-wired system bus.......................................................................................... 22 6.5. EEPROM access by 2-wired system bus ....................................................................................... 23 6.6. Operation mode selection using external terminals......................................................................... 24 6.7. System connection example ......................................................................................................... 25 7. Additions ......................................................................................................................................... 26
7.1. Figure of video amplifier frequency characteristics ................................................................... 26 8. Packagedimensions........................................................................................................................... 28
LR36B15 2
1. Description
This product is the LSI equipped with the AFE block contain CDS, PGA and ADC, drive timing pulse generator of the 270-thousand to 470-thousand pixels CCD area sensor, each pulse generator for the television signal, the signal processing function for converting to the video signal from the CCD image converted to digital signal and 75ohm video amplifier contains LPF.
・Features
AFE for CCD
• 12bit AD convertor with CCD I/F • CDS of 1Vpp input range • Input clamping circuit
• PGA of gain range from -3dB to 36dB • Black level calibration circuit
Timing generator for CCD (TG)
• It corresponds to the CCD of 270-thousand and 410-thousand pixels for NTSC, 320-thousand 470-thousand pixels for PAL.
Image signal processor (ISP)
• The automatic exposure control function is equipped. • The automatic white balance control function is equipped. • The automatic carrier balance equalizer function is equipped. • The line crawl compensation function is equipped. • The white blemish compensation function is equipped.
• The gamma correction functions for brightness signal and the color signal are equipped independently. • Lens shading compensation function is equipped. • It has the output of the DC IRIS control.
• 50Hz flicker suppression function is equipped.
Video encoder
• Correspond to NTSC-M, PAL-BDG video format. • Support standard composite video format. • 10-bit DA convertor is equipped.
• 75-ohm drive amplifier of 6dB gain with LPF is equipped. • SAG correction function is equipped.
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Others • 4K bit EEPROM Read/Write function for the adjustment parameter storage. (LR36B15 needs EEPROM which has 16 or more bytes page access feature). • Host interface is dedicated 2-wired serial interface. • 1.8V linear regulator is equipped. (3.3V single power supply) • NTSC:28.63636MHz / PAL:28.375MHz crystal oscillator is equipped. • Small QFN package (HQFN-P-0909-0.5, Pb free, Halogen free) • Operation temperature : -30 to 85 °C 2. Pin Assignment TEST0 CCDIN REFIN OBCAP1 OBCAP0 VCM VRP VRN AVDD3 AVSS AVDD IREF DREF ATIO2 ATIO1 AVSS MONITOR TEST5 TEST4 TEST3 TEST2 TEST1 DVSS FVDD FH1 FH2 FR DVSS PVDD V1XD V2XD V3XD 49505152535455565758596061626348 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TOP VIEW1PIN MARK
V4XD VH1XD VH3XD OFDXD DVDD DVSS PVDD EE WB1 WB2 BLC MIR WEIGHT MCHRO TESTO0 HD_CSYNC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32313029282726252423222120191817SAG VIDEO XVDD XTI XVSS XTO RSTN SCL SDA EEPCK EEPDA TEST6 PVDD DVSS TESTO1 VD LR36B15 4
3. Pin Description No. Name PS I/O type (*1) (*2) Function Vertical CCD clocking pulse. Connect to V-driver. 1 V4XD P O_2 Output high at reset. Pixel transfer gate pulse. Connect to V-driver. 2 VH1XD P O_2 Output high at reset. Pixel transfer gate pulse. Connect to V-driver. 3 VH3XD P O_2 Output high at reset. OFD(Over Flow Drain) pulse. Connect to V-driver. 4 OFDXD P O_2 Output high at reset. LDO decoupling terminal for internal digital circuit power supply. 5 DVDD D － Connect 2.2μＦ capacitor between DVSS. Ground terminal. 6 DVSS P － Power supply for digital I/O buffer. (3.3V) 7 PVDD P － 8 EE P IO_2 Fixed speed of an electrical shutter mode selection terminal 9 WB1 P IO_2 Fixed white balance mode setting terminal 1. 10 WB2 P IO_2 Fixed white balance mode setting terminal 2. 11 BLC P IO_2 Backlight compensation mode selection terminal. 12 MIR P IO_2 Mirror mode selection terminal. 13 WEIGHT P IO_2 AE weight parameter selection terminal. 14 MCHRO P IO_2 Color suppression mode selection terminal. Test terminal. 15 TESTO0 P O_2 Please do not connect it anywhere. Horizontal synchronous signal or composite synchronous signal 16 HD_CSYNC P IO_2 output terminal. Output low at reset. Vertical synchronous signal output terminal. 17 VD P IO_2 Output low at reset. Test terminal. 18 TESTO1 P O_2 Please do not connect it anywhere. Ground terminal. 19 DVSS P － Power supply for digital I/O buffer. (3.3V) 20 PVDD P － Test mode setting terminal. 21 TEST6 P IS Connect to DVSS. (Pull-down) EEPROM serial data I/O terminal. 22 EEPDA P IOS_3 Connect data terminal of EEPROM with pull-up resister.(*3) EEPROM serial clock output terminal. 23 EEPCK P O_3 Connect clock terminal of EEPROM with pull-up resister. (*3) Data input terminal from the external host to adjust camera 24 SDA P IOS_3 parameters. (*3)
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No. Name PS I/O type (*1) (*2) Function Clock input terminal from the external host to adjust camera 25 SCL P IS parameters. Reset signal input terminal. 26 RSTN P IS L : Reset / H : Normal operation Hi-Z condition is forbidden for this terminal. Clock oscillator output. 27 XTO X OSC_O CKI and CKO make oscillator circuit. Ground terminal. 28 XVSS X － Clock oscillator input. 29 XTI X OSC_I Crystal oscillator’s frequency (NTSC:28.63636MHz PAL:28.375MHz) 30 XVDD X - Power supply for analog circuit. (3.3V) Video signal output terminal. 31 VIDEO X O_A Refer to 7.1 video amplifier frequency characteristics for connection with SAG terminal. SAG correction control terminal. 32 SAG X O_A Refer to 7.1 video amplifier frequency characteristics for connection with VIDEO terminal. 33 AVSS X - Ground terminal. 34 ATIO1 X O_A Analog I/O for testing. Connect to AVSS. 35 ATIO2 X O_A Analog I/O for testing. Connect to AVSS. Reference voltage for DAC decoupling terminal. 36 DREF A3 O_A Connect 1μF capacitor between AVSS. Output low at reset. Bias current for internal analog circuit output terminal. 37 IREF A3 O_A Connect 8.2kΩ resister between AVSS. Output Hi-Z at reset. LDO decoupling terminal for internal analog circuit power supply. 38 AVDD A3 － Connect 2.2μＦ capacitor between DVSS. Ground terminal. 39 AVSS A3 － Power supply for analog circuit. (3.3V) 40 AVDD3 A3 － Reference voltage for ADC decoupling terminal. Connect 1μF capacitor between VRP and connect 1μF capacitor 41 VRN A3 O_A between AVSS. Output Hi-Z at reset. Reference voltage for ADC decoupling terminal. Connect 1μF capacitor between VRN and connect 1μF capacitor 42 VRP A3 O_A between AVSS. Output Hi-Z at reset. Common voltage for ADC decoupling terminal. 43 VCM A3 O_A Connect 1μF capacitor between AVSS. Output Hi-Z at reset. Black level integrated voltage output terminal. 44 OBCAP0 A3 O_A Connect 1μF capacitor between AVSS. 45 OBCAP1 A3 O_A Output Hi-Z at reset. Referencesignalinput terminal.46 REFIN A3 I_A Connect 1μF capacitor between AVSS. 47 CCDIN A3 I_A CCD signal input terminal. Test mode setting terminal. 48 TEST0 A3 I_A Connect to AVSS. (Pull-down)
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No. Name PS I/O type (*1) (*2) Function Monitor signal output terminal for DC IRIS. 49 MONITOR A3 O_A Output Hi-Z at reset. Test mode setting terminal. 50 TEST5 F I Connect to DVSS. (Pull-down) Test mode setting terminal. 51 TEST4 F I Connect to DVSS. (Pull-down) Test mode setting terminal. 52 TEST3 F I Connect to DVSS. (Pull-down) Test mode setting terminal. 53 TEST2 F I Connect to DVSS. (Pull-down) Test mode setting terminal. 54 TEST1 F I Connect to DVSS. (Pull-down) Ground terminal. 55 DVSS F － Power supply for CCD horizontal driver. (3.3V) 56 FVDD F － Horizontal CCD’s driving pulse. Connect to CCD. 57 FH1 F O_16 (Several CCD may need level converter) Output Hi-Z at reset. Horizontal CCD’s driving pulse. Connect to CCD. 58 FH2 F O_16 (Several CCD may need level converter) Output Hi-Z at reset. Output gate resetting pulse. Connect to CCD via capacitor. 59 FR F O_8 Output Low at reset. Ground terminal. 60 DVSS P － Power supply for digital I/O buffer. (3.3V) 61 PVDD P － Vertical CCD clocking pulse. Connect to V-driver. 62 V1XD P O_2 Output high at reset. Vertical CCD clocking pulse. Connect to V-driver. 63 V2XD P O_2 Output high at reset. Vertical CCD clocking pulse. Connect to V-driver. V3XD P O_2 Output high at reset. (*1) D means DVDD, A3 means AVDD3, X means XVDD, P means PVDD, F means FVDD (*2) I/O type is as follows; (*3) Decide pull-up resister value to meet the condition that the sink current 3mA at VOL=0.4V.
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Symbol I/O type IS Schmidt level input terminal I CMOS level input terminal I_D CMOS level input terminal (pull-down resister contained) I_A Analog input terminal IO_2 Input and output terminals CMOS level input Capable output current is 2mA (when the power is 3.3V) IO_A Analog input and output terminal IOS_3 Input and output terminals schmidt level input Capable output current is 3mA (when the power is 3.3V) O_2 Output terminals Capable output current is 2mA. (when the power is 3.3V) O_3 Output terminals Capable output current is 3mA. (when the power is 3.3V) O_8 Output terminals Capable output current is 8mA. (when the power is 3.3V) O_16 Output terminals Capable output current is 16mA. (when the power is 3.3V) O_A Analog output terminal OSC_I Input terminal for the oscillation circuit OSC_O Output terminal for the oscillation circuit
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4. Block Diagram OBCAP1 OBCAP0 MONOUT DVDD AVDD IREF DREF VCM VRP VRN REF LDO CLPCCDIN From CCD REFIN VAMP LR36B15 9 Detail block diagram of ISP and video encoder block Separationluminance andcolor signal Y Luminance signalprocessing gamma correction,aperture correction(V,H)Video encoder Color signal processing RGB gamma correction,color suppression,color space conversion,white balanceDACSRAM(Delay RAM) R,G,BYLAutomatic exposurecontrol(Shutter speed, AGC)TG SSGAFE(PGA setting) ・Sampling pulsed for ADC, clamp pulse・CCD drive signal・V-driver timing signalI2C Master (EEPROM I/F)ArbitrationcircuitI2C Slave( External hostI/F)ExternalEEPROM External host LR36B15 10 5. Electrical characteristics 5.1. Absolute maximum ratings Parameter SymbolMin. Max. Units Notes Power voltages for digital I/O PVDD -0.3 4.3 V Power voltages for CCD FVDD -0.3 4.3 V horizontal driver Power voltages for analog circuit1 AVDD3-0.3 4.3 V Power voltages for analog circuit2 XVDD-0.3 4.3 V External voltages for DVDD DVDD-0.3 2.3 V terminal (*1) External voltages for AVDD AVDD-0.3 2.3 V terminal (*1) Input voltages for digital I/O PVDD+0.3 VIP -0.3 V (*2)terminals or 4.3V Analog input voltages 1 (*3) AVDD3+0.3 VIA3 -0.3 V or 4.3V Analog input voltages 2 (*4) XVDD+0.3 VIX -0.3 V or 4.3 Output voltages for digital I/O PVDD+0.3 VOP -0.3 V (*5)terminals or 4.3V Output voltages for CCD FVDD+0.3 VOF -0.3 V (*6)horizontal drivers or 4.3V Analog output voltages 1 (*7) AVDD3+0.3 VOA3 -0.3 V or 4.3V Analog output voltages 2 (*8) XVDD+0.3 VOX3 -0.3 V or 4.3 Storage temperature TSTG -65 150 ℃ (Note) Exceeding any of the above limiting values may result in permanent device damage. Normal function will not be guaranteed after any the above limiting values is exceeded. (*1) Regulator output terminal. When the voltage that is higher than maximum value is forced, this LSI will be reset. (*2) Applied to PVDD power supplied input terminals (I, IS) and I/O terminals (IO_2). (*3) Applied to AVDD3 power supplied input terminals. (*4) Applied to XVDD power supplied input terminals. (*5) Applied to PVDD power supplied output terminals (O_2) and I/O terminals (IO_2). (*6) Applied to FVDD power supplied output terminals (O_8, O_16). (*7) Applied to AVDD3 power supplied output terminals. (*8) Applied to XVDD power supplied output terminals. LR36B15 11 5.2. Recommended operating conditions Parameters Symbol Min.Digital I/O PVDD 3.15power supply voltage CCD horizontal driver FVDD 3.15power supply voltage Analog power supply AVDD3 3.15voltage1 Analog power supply XVDD 3.15voltage2 Input clock Operating temperature CKI Ta 10 -30 Typ. Max.Units Notes 3.3 3.6 V 3.3 3.3 3.3 28.636 (*1) 28.375 (*2) 25 3.6 V 3.6 3.6 V V PVDD=FVDD= AVDD3=XVDD (*1) NTSC 30 MHz (*2) PAL 85 ℃ (Note) Power supply voltages are based on each ground terminal levels. All of the ground terminals should be same level. (AVSS=DVSS=XVSS=0V). LR36B15 12 5.3. DC characteristics (PVDD=FVDD=3.15~3.6V, DVSS=0V, Ta=-30~85℃) Parameter SymbolMin. Typ.Max. Units Notes Hi leval digital input voltage 1 (*1) VIH1 0.8PVDD V (*1) Lo level digital input voltage 1 VIL1 0.2PVDD V Hysteresis voltage (*2)VHIS 0.05PVDD V (*3) Digital output Hi voltage 1 VOH10.8PVDD V =IOH -2mA Digital output Lo voltage 1 (*3) VOL1 0.2PVDD V IOL= 2mA Digital output Hi voltage 2 (*4) VOH20.8FVDD V =IOH -8mA Digital output Lo voltage 2 (*4) VOH2 0.2FVDD V IOL= 8mA Digital output Hi voltage 3 (*5) VOH30.8FVDD V =IOH -16mA Digital output Lo voltage 3 (*5) VOH3 0.2FVDD V IOL= 16mAEEPCK, EEPDA, SDA VOLC 0.4 V =IOLC3mA Lo output voltage Digital input Hi leakage 1 (*1) IHL1 -10 10 uA =VINPVDD (*1) Digital input Lo leakage 1 ILL1 -10 10 uA =VIN0 V (*1) EE, WB1,2, BLC, MIR, WEIGHT, MCHRO, EEPDA, SCL, SDA, RSTN (*2) SDA, SCL, EEPDA (*3) V1XD~V4XD, VH1XD, VH3XD, OFDXD, HD_CSYNC, VD (*4) FR (*5) FH1, FH2 LR36B15 13 5.4. Analog characteristics 5.4.1. AFE block (Conditions : AVDD3=XVDD=3.3V, AVSS=0V, Ta=25℃) (Unless otherwise specified: ADC sampling frequency = 15MHz, Input frequency = 1MHz, Input level = 1.0Vpp) Parameter Min. Typ. Max. UnitsConditions Measured downward from clamp voltage. Input range (*1) 0.8 1.0 Vpp With settings of black level code = 0, PGA gain = 0dB. CCDIN ~ ADC Input bandwidth 1 pixelADC settling time for step input of full scale -2dB. With setting of PGA gain = 0dB. Clamp voltage 1.3 1.4 1.5 V CCDIN and REFIN terminal voltage in CLP active.VRP voltage 1.3 1.4 1.5 V VRN voltage 0.4 0.5 0.6 V PGA minimum gain -4.1 -3.1 -2.1 dB Value relative to 0dB setting. PGA maximum gain 35.4 36.4 37.4 dB PGA resolution 0.0 0.05 0.10 dB Black calibration At sampling frequency = 15MHz bandwidth 547 us With setting of x1 (default) (Time Constant) (*2) 0.13 us With setting of x4096 (*1) CCDIN input level when ADC output reaches FFFh. (*2) Black calibration bandwidth can be set from x1 to x4096, 12steps by register setting. And it will be change according to operation frequency as follows, τ [sec] ≡ 8200 / (Fs [Hz] x (speed setting)) LR36B15 14 Parameter Min. Typ. Max. Units MONITOR output gain (*3)MONITOR output bandwidth (*4) -2 0 +2 dB Conditions ADC Resolution ADC diff. nonlinearity ADC Integ. nonlinearity AFE total Noise (*6) REFIN, CCDIN ~ MONOUT WINDOW = L (internal signal), (*6) -7 dB Amplitude difference between input frequency is 190k and 1MHz WINDOW = H (internal signal), -1 dB Amplitude difference between input frequency is 1M and 4MHz (*5) 12 bit ±1.5 +3 / <-2.0 ±6 LSB LSB LSB rmsLSB rmsLSB rmsWith setting of PGA gain = 0dB With setting of PGA gain = 18dB With setting of PGA gain = 30dB 0.9 2.2 8.4 (*3) Amplitude difference between MONITOR terminal output and CCDIN terminal input sine wave ingredient signal. With load of CL=30pF to MONITOR terminal. (*4) Monitor terminal output amplitude difference between two input frequencies. With load of CL=30pF to MONITOR terminal. (*5) Guarantee no missing code in 11bit precision. Range of from -255 to 4095. (*6) “WINDOW” is internal signal generated in ISP block. Set with following registers WIN_PS (01E[7:0]), WIN_PE (083[7:0]), WIN_LS (0A7[7:0]) and WIN_LE(0FD[7:0]). Fixed Lo in Default. LR36B15 15 5.4.2. Analog output block (Conditions : AVDD3=XVDD=3.3V, AVSS=0V, Ta=25℃) (Unless otherwise specified: DAC sampling frequency = 28MHz) Parameter Min. Typ. Max. Units Conditions DAC resolution 10 bit DAC diff. nonlinearity ±0.6 ±2.0 LSB (*1) DAC integ. nonlinearity ±0.4 ±1.0 LSB (*1) Video amplifier output gain 5.0 6.0 7.0 dB Amplifier input level = 1Vpp (*2) (*3)Video amplifier full scale voltage 2.0 2.6 Vpp Video amplifier LPF ripple -1 ±0.5 +1 dB Bandwidth 100kHz ~ 5.5MHz Video amplifier LPF group delay 6 30 ns |GD 3MHz – GD 5.5MHz| (*4) Analog output total S/(N+D) 45 51 dB Bandwidth 100kHz ~ 5.5MHz (*5) Analog output total S/N 54 dB Bandwidth 100kHz ~ 5.5MHz (*5) (*1) DAC output of ramp wave. (input code : 0 ~ 1023) (*2) Amplifier input level 1Vpp correspond to DAC output when input code is from 0 to 800. (*3) Distortion characteristic is not guaranteed when output over 2.0Vpp. (*4) Design reference value. (*5) Video amplifier output when the digital sine wave signal of 1MHz and 1Vpp is input to DAC. Output load resistance : 150Ω, Output load capacitance : 15pF [Measurement circuit] LSI SAGVIDEO150Ω15pFMeasurement nodeSAG correction is not use LR36B15 16 5.4.3. Crystal oscillator (Conditions : XVDD=3.3V, XVSS=0V, Ta=25℃) Parameter Min. Typ. Max. Units Conditions Oscillation frequency 28.636 28.375 ±10 13 2 MHz ±100 ppm pF 100 Ω pF NTSC PAL (*2) Frequency accuracy Load capacitance CL Effective equivalent resistance Re Crystal parallel capacitance CO XTI terminal external connection 22 pF When use CL=13pF crystal load capacitance CXI XTO terminal external connection 22 pF When use CL=13pF crystal load capacitance CXO Recommended crystal is CA-301 (EPSON TOYOCOM). (*1) Effective equivalent resistance generally may be taken as Re = R1×(1+C0/CL)2 , where R1 : Crystal series equivalent resistance, C0: Crystal parallel capacitance, CL: Load capacitance Example connection Rf XTI pin XTO pinLSI internal circuit External circuitRd (* 2) CXI=22pF CXO=22pF (*2) Determine need for and appropriate value of limiting resistance (Rd) in accordance with the crystal specifications. LR36B15 17 5.4.4. Regulator block (Conditions : AVDD3=PVDD=3.3V, AVSS=DVSS=0V, Ta=25℃) Parameter Min. Typ. Max. Units Conditions Output Voltage Maximum output (Limit current) Over voltage detection voltage (*1) 1.75 1.80 1.85 V 1.85 1.90 1.95 V 67 > 2.3 87 2.4 114 mA V For digital For analog For digital and analog For digital and analog (*1) When over voltage is detected, the LSI will be reset. LR36B15 18 5.5. AC timing 5.5.1. 2-wired serial system bus I/O timing (Typical conditions : PVDD=3.3V, DVSS=0V, Ta=25℃) (Minimum and maximum conditions : PVDD=3.15 ~ 3.6V, DVSS=0V, Ta=-30 ~ 85℃) SDA / EEPDA tF SCL / EEPCK tR VIHVILtLOW tSU :STA tBUF tHD STA : tR tFtSU : VIHVILParameter Symbol Min. Max. Units Bus Free Time Hold Time (Start Condition) Clock Pulse Low Time Input Signal Rise Time Input Signal Fall Time Setup Time(Start Condition) Setup Time(Stop Condition) tBUF tHD:STA tLOW tR tF tSU:STA tSU:STO 1.3 0.6 1.3 0.6 0.6 300*1 300*1 usec usec usec nsec nsec usec usec *1 Do not inspect in mass production. LR36B15 19 SDA / EEPDA tHIGH SCL / EEPCK tHD :DATVIH VIL VIH VIL TSU :DAT Parameter Symbol Min. Max. Units Data Setup Time Data Hold Time Clock Pulse High Time tSU:DAT tHD:DAT tHIGH 100 0.0(*1) 0.6 0.9(*2) nsec usec usec (*1) The device should internally possess the hold time of 300ns or more for the SDA signal, and escape indeterminate condition in SCL falling edge. (*2) This condition must be met if this LSI used with tLOW=1.3us. LR36B15 20 5.5.2. Reset pulse tRST/tRJCT RSTN Parameter Symbol Min. Typ. Max. Units Conditions RSTN pulse width tRST 500 nsec RSTN rejection pulse width tRJCT 50 nsec 5.5.3. Power ON/OFF sequences The power supply is turned on according to the following procedures. Procedure Power Regulator XTAL Reset Note Before turning on the power OFF supply OFF Stop ① PVDD,FVDD turning on Low Rising ② Regulator ③ XTAL Oscillation ON ④ V driver power supply (*1) ON turning on Oscillation L→High (*2) ⑤ Reset release High ⑥ Parameter setting (*1) Please turn it on after the low input of V-driver becomes under 0.5V and the high input of it becomes over the VDD (TYP:3.3V) - 0.5V. (*2) Please do the reset release and turn on ΦV after the clock is steady and the VL (-8V) become under the VL * 0.9. Note 3) When re-turning on, please wait till the VL become over the VL * 0.1 after the each power supply turn off. And then, please do the above sequence. Turn on sequence (1) PVDD,FVDD (2) Regulator (4)V-driver (+15V) (-8V) (3)XTAL (5)Reset ΦV(VdrOUT) ΦH, ΦR (6)Parameter setting reset Turn off sequence LR36B15 21 6. System Architecture 6.1. CCD Sensor This LSI has a timing generation circuit and a voltage change circuit, and then this is enable to drive the following CCD sensor. (Some CCD is used with external circuit of Amplifier transmitter of horizontal drive pulse.) Supported sensor 270-thousand pixels CCD sensor for NTSC 410-thousand pixels CCD sensor for NTSC 320-thousand pixels CCD sensor for PAL 470-thousand pixels CCD sensor for PAL Register settings (Adrs:001h) TVMD (bit5) SCCD (bit4) 0 0 0 1 1 0 1 1 6.2. Host I/F At the host I/F that the following serial bus was connected with, it can set a parameter for the various setting. Serial bus 2-wired system bus Terminal used Rate (Max) 400kbps Reference standard Standard Mode I2C-BUS ( I2C-BUS SPECIFICATION Ver2.1: Jan.2000) SCL SDA Slave address is “1010000Xb” fixed. 6.3. EEPROM It controls EEPROM which the following serial bus was connected with to save or load of the parameter for the all kind setting in the DSP can be done. Also, each parameter can be automatically read in case of start-up. Incidentally, in case of saving / loading to EEPROM, this DSP accesses EEPROM continuously in 16 bytes, being the longest. Therefore, EEPROM use the one which has the page write feature of equal to or more than 16 bytes. Serial bus 2-wired system bus Terminal used Rate (Max) Reference devices EEPCK M24C04 (ST-MICRO) 400kbps 24LC04B (MICROCHIP) EEPDAI Slave address of EEPROM can be set in DSP adrs 2D3h and 2E3h. LR36B15 22 6.4. Host I/F access by 2-wired system bus Host I/F by the 2-wire system bus of this LSI writes to an outside host according to a logical form, and provides the function to read. Host I/F by the 2-wire system consists of clock line (SCL) for serial communications and serial data line (SDA). (1) Data writing format to the DSP for byte. SCL SDA S M T S B Slave Device address Write register Data W Register address L A MS C S B K BLAMSCSBKB LASSCPBK Direction of the data transfer: □ external host ⇒this LSI ■ this LSI ⇒external host (2) Data reading format from the DSP for 1 byte. SCL Slave Device W Register address SDA address S M T S B L A M S C S B K B LASCBK RRead register Data AM CSKB Slave Device address R M S ST B L SBL N S S A P B • Start bit (ST) : It is provide for start communication. • Slave Device address : Slave Device for communication is provide • ACK bit,NACK bit (NA) : The bit for handshaking in one bit is followed 8 bit data (slave device address, register address, and register data). • Register address (8bit) : Receive data. It specified the lower 8bit inside of 12bit address. • Register data (8bit) : Send and receive data. Read/ Write value of register. • Stop bit (SP) : It is provide for stop communication. • Resta bit (RST) : It is provide for start reading. ○Start bit (START), Restart bit (RESTA), Stop bit (STOP) Start bit and Restart bit are defined that the data line (SDA) changes low level from high level with the clock line (SCL) keeping high level. Stop bit is defined that the data line (SDA) changes High level from Low level with the clock line (SCL) keeping high level ○ACK bit, NACK bit The following one bit of 8 bit data (slave device address, register address, and register data) is a bit for handshaking. When 8 bit data is normally received, the device that receives 8 bit data generates ACK bit (Active Low). At this time, the other device where 8 bit data was transmitted opens the data line. When the host is communicating with other slave devices and 8 bit data cannot be normally received, this device opens the data line and generates NACK bit (Active High) with an external pull-up resistor. Note) Setting of bank switching is in MSADR register (adrs xFFh). LR36B15 23 6.5. EEPROM access by 2-wired system bus In the setting of the following registers, a set value of each register of DSP is written in EEPROM, the register of DSP can be set from EEPROM. Register setting value Address 02F9h 00h No Operation (default) 03h DSP→EEPROM Batch data writing 0Ch EEPROM→DSP Set data reading This LSI will reload DSP setting data from EEPROM when power up sequence (after reset release). Relation between EEPROM condition and register access after automatic reload is as follows. EEPROM→DSP DSP←Host DSP→EEP EEPROM Auto. reload ROM Read Data Read Access Write Access when power up (1) Initialized Valid Enable Enable Enable Enable Not (2) Invalid dataDisable initialized In case of the EEPROM which is not initialized is connected, the DSP may set in condition (2). Please initialize EEPROM according to following sequence. [Initialize EEPROM] proceHost→DSP operation Contents ss Adrs R/W Value 1 02F9h Read (‘00h’) 2 02F9h Write (‘03h’) Initialize EEPROM 3 02F9h Read (‘00h’) (During adrs 02F9h[4]=’1’, DSP accessing to EEPROM. Do not 4 02F9h Write (‘03h’) do next sequence until it turn to ‘0’.) 5 02F9h Read (‘00h’) 6 Make reset or turn off the power of LSI once and turn it on again. 7 02F9h Read (‘00h’) Confirm to finish accessing to EEPROM. 8 any Write Any Write data to EEPROM after the parameter that is wanted to 9 02F9h Write (‘03h’) store to EEPROM are set to DSP. 10 02F9h Read (‘00h’) Confirm to finish EEPROM access. LR36B15 24 6.6. Operation mode selection using external terminals To set register SW_SEL (adrs 018h[0]) =’0’, external terminal witch has function same as corresponded registers will be active. Operation mode Terminal EE Mode description Fixed speed of an electronic shutter 0: Fixed Shutter speed (NTSC: 1/100, PAL: 1/120 correspond to REG_EEMD=0001) 1: Automatic shutter speed control Fixed white balance mode 00: Fixed mode WB1 01: Fixed mode WB2 10: Fixed mode WB3 11: Automatic control Backlight compensation mode 0: Normal 1: Backlight Mirror mode 0: Normal 1: Mirror Weight parameter selecion 0: A 1: B A: set in adrs 111h~117h B: set in adrs 0EBh~0F1h White and black video output 0: Normal (color) 1: White and black video output Priority of terminal setting and register setting. Selected by SW_SEL register (adrs 018h[0]) SW_SEL= ”0” (Default) SW_SEL= “1” EE terminal is active REG_EEMD (adrs 019h[7:4]) is active REG_WBSEL (adrs 0x19[3:2]) is active REG_BLC (adrs 019h[1]) is active REG_MIR (adrs 019h[0]) is active REG_WEIGHT (adrs 0EB[5]) is active REG_MCHRO (adrs 0x21[7]) is active WB1,2 WB1,2 terminals are active BLC MIR BLC terminal is active MIR terminal is active WEIGHT WEIGHT terminal is active MCHRO MCHRO terminal is active LR36B15 25 6.7. System connection example PVDDPVDDpull uppull upMicro Processor 2(IC Controller) EEPROM (IC Controller) 2CCD IN 1uF SDA SCLCCDIN REFIN RSTNEEPDA EEPCKVD HD_CSYNC TESTO1 1uF OBCAP0 OBCAP1 EE MCHRO WB1,2 MIR WEIGHT 1uF 1uF Terminal Settings IREF DREF VRP 1uFVRN 1uF 1uF 1uF 8.2kΩ VCM 1uF XTI 22pFLSI XTO 22pF Video Output (*1) VIDEO SAG PVDD TEST[0:6] 0.1uF PVDD 10uF AVDD3 AVDD3 0.1uF 10uF DVSS FVDD AVSS FVDD 0.1uF 10uF XVDD XVDD 0.1uF 10uF XVSS DVDD DVSS2.2uF Analog GND Digital GNDAVDDAVSSV1XD ~ V4XD VH1XDVH3XDOFDXDV driver DVSS FH1 FH2 FR CCD sensor 2.2uF (*1) Refer to figure of video amplifier frequency characteristics for connection between VIDEO and SAG terminal. LR36B15 26 7. Additions 7.1. Figure of video amplifier frequency characteristics (a) SAG compensation is used : 47uF + 1uF Video Out 75Ω 47uF LSI VIDEO 75Ω SAG 1uF (b) SAG compensation is not used : 200uF Video Out 75Ω 200uF LSI VIDEO Measurement point is Video Out 75Ω SAG (c) SAG compensation is not used : 100uF Video Out 75Ω 100uF LSI VIDEO 75Ω SAG (Unless otherwise Ta=25℃, AVDD3=3.3V, Design reference value) (a) 1uF+47uF (b) 200uF(c)100uF10(a) (b) Gain [dB]05.5MHz-10(C) -20-30-401.E+001.E+011.E+021.E+031.E+041.E+05周波数 [Hz] (log)1.E+061.E+071.E+08 8 Package and packing specification [Applicability] This specification applies to an IC package of the LEAD-FREE delivered as a standard specification. 1.Storage Conditions. 1-1.Storage conditions required before opening the dry packing. Normal temperature : Normal humidity : ( Relative humidity) max. Storage periodOne year max. *\"Humidity\" means \"Relative humidity\" 1-2.Storage conditions required after opening the dry packing. In order to prevent moisture absorption after opening, ensure the following storage conditions apply: 1Storage conditions for one-time soldering. (Convection reflow*1, IR/Convection reflow.*1) Temperature : Humidity : max. Period : 96 hours max. after opening. (2) Storage conditions for two-time soldering. (Convection reflow*1, IR/Convection reflow.*1) a. Storage conditions following opening and prior to performing the 1st reflow. Temperature : Humidity : max. Period : 96 hours max. after opening. b. Storage conditions following completion of the 1st reflow and prior to performing the 2nd reflow. Temperature : Humidity : max. Period : 96 hours max. after completion of the 1st reflow. *1 :Air or nitrogen environment. 2. Baking Condition. 1Situations requiring baking before mounting. Storage conditions exceed the limits specified in Section 1-2 2Recommended baking conditions. Baking temperature and period : 125 for 25 hours. The above baking conditions apply since the trays are heat-resistant. 3Storage after baking. After baking, store the devices in the environment specified in Section 1-2 and mount immediately. 27 20110727 3. Surface mount conditions. The following soldering conditions are recommended to ensure device quality. 3-1.Soldering. 1Convection reflow or IR/Convection reflow. (one-time soldering or two-time soldering in air or nitrogen environment) Temperature and period : A) Peak temperature. 250 max. B) Heating temperature. 45 to 65 seconds as 220 C) Preheat temperature. It is 150 to 180, and is 105±15 seconds D) Temperature increase rate. It is 1 to 3/seconds Measuring point : IC package surface. Temperature profile : A B C D Time 4. Condition for removal of residual flux. 1Ultrasonic washing power : 25 watts / liter max. 2Washing time : Total 1 minute max. 3Solvent temperature : 1540 5. Package outline specification. 5-1Package outline. Refer to the attached drawing. (Plastic body dimensions do include burr of resin.) 5-2Package weight. 0.2g/pcs. About. 6. Markings. 6-1.Marking details. (The information on the package should be given as follows.) 1Product name LR36B15 2Company name SHARP 3Date code ExampleYYWWXXX YY Denotes the production year. (Last two digits of the year.) WW Denotes the production week.01025253 XXX Denotes the production ref. code. 6-2.Marking layout. The layout is shown in the attached drawing. (However, this layout does not specify the size of the marking character and marking position.) IC package surface temperature 28 20110727 29 PKG HQFN0-P-0909 UNIT NOTE mm20110727 7.Packing Specifications (Dry packing for surface mount packages.) 7-1.Packing materials. Material name Material specifications Inner carton Cardboard 2600 devices / inner carton max. Tray Conductive plastic260 devices / tray Upper cover tray Conductive plastic1 tray / inner carton Laminated aluminum Aluminum polyethylene bag Desiccant Silica gel Label Paper PP band Polypropylene 3 pcs. / inner carton Outer carton Cardboard 10400 devices / outer carton max. Devices must be placed on the tray in the same direction. 7-2.Outline dimension of tray. Refer to the attached drawing. 8. Precautions for use. (1) Opening must be done on an anti-ESD treated workbench. All workers must also have undergone anti-ESD treatment. (2) The trays have undergone either conductive or anti-ESD treatment. If another tray is used, make sure it has also undergone conductive or anti-ESD treatment. (3) The devices should be mounted within one year of the date of delivery. 9. Chemical substance information in the product 30 Purpose Packing the devices. 10 trays / inner carton Securing the devices. Securing the devices. Keeping the devices dry. Keeping the devices dry. Indicates part number, quantity, and packed date. Securing the devices. Outer packing. 20110727 UNITmm 31 20110727 32 DRAWING NO. BJ433c UNIT mm 20110727 33 DRAWING NO. BJ433d UNIT mm 20110727 34 (Note) The << LEAD FREE >> display shows a lead free article. \"R.C.\" is Sharp's corporate logo indicating that the product is RoHS compliant. (a) < LEAD FREE > (e) (b) (j) < LOT >xxxxxxxxxx xxxx (c) (d) SHARP (f)(g)(h)(i) Outer carton label < LEAD FREE > (c) (e) (g) (d) (a) (k) (f) $TD (a) (b) (c) (d) (e) (f) “SHARP” Logo 20110727
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