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Freescale Semiconductor

Technical Data

Document Number:MPC8272EC

Rev. 2, 12/2008

MPC8272

PowerQUICC II™ FamilyHardware Specifications

This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC8272 family of

devices—the MPC8272, the MPC8248, the MPC8271, and the MPC8247. These devices are .13µm (HiP7) members of the PowerQUICCII™ family of integrated communications processors. They include on a single chip a 32-bit

PowerPC™core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set; a modified

communications processor module (CPM); and an integrated security engine (SEC) for encryption (the MPC8272 and the MPC8248 only).

All four devices are collectively referred to throughout this hardware specification as “the MPC8272” unless otherwise noted.

1.2.3.4.5.6.7.8.9.10.11.

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 9Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 12Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 16Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 25Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 57Document Revision History . . . . . . . . . . . . . . . . . . . 57

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Overview

1Overview

Table1. MPC8272 PowerQUICC II Family Functionality

Devices

Functionality

Package 1

Serialcommunicationscontrollers(SCCs)QUICC multi-channel controller (QMC)

Fastcommunicationcontrollers(FCCs)I-Cache (Kbyte)

3Yes21616210Yes——1Yes

3Yes21616200Yes——1Yes

MPC8272

MPC8248

MPC8271

MPC8247

Table1 shows the functionality supported by each device in the MPC8272 family.

516 PBGA

3Yes21616210Yes——1—

3Yes21616200Yes——1—

D-Cache (Kbyte) Ethernet(10/100)

UTOPIAIIPorts

Multi-channel controllers (MCCs) PCI bridge

Transmission convergence (TC) layer

InversemultiplexingforATM(IMA)Universal serialbus(USB)2.0full/lowrate

Security engine (SEC)

Refer to Table2.

Devices in the MPC8272 family are available in two packages—the VR or ZQ package—as shown in Table2. For package ordering information, refer to Section10, “Ordering Information.”

Table2. MPC8272 PowerQUICC II Device Packages

Code(Package)

(516 PBGA—Lead free)

MPC8272VR

Device

MPC8248VRMPC8271VRMPC8247VR

(516 PBGA—Lead spheres)

MPC8272ZQMPC8248ZQMPC8271ZQMPC8247ZQ

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Overview

Figure1 shows the block diagram of the MPC8272.

16 KbytesI-CacheI-MMUG2_LE CoreSecurity (SEC)1System Interface Unit (SIU) 60x Bus16 KbytesD-CacheD-MMUBus Interface Unit60x-to-PCI BridgeMemory ControllerPCI Bus32 bits, up to 66 MHzCommunication Processor Module (CPM) TimersParallel I/OBaud RateGenerators4 KBInterrupt Instruction ControllerRAM16 KBDataRAMClock CounterSerialDMAVirtualIDMAsSystem Functions32-bit RISC Microcontrollerand Program ROMFCC1FCC2SCC1SCC3SCC4SMC1SMC2SPII2CUSB 2.0Time Slot AssignerSerial interfaceSerial Interface2 TDM Ports2 MII/RMII Ports1 8-bit UtopiaPort2Non-MultiplexedI/ONote

1 MPC8272/8248 only2 MPC8272/8271 only

Figure1. Block Diagram

1.1Features

The major features of the MPC8272 are as follows:•Dual-issue integer (G2_LE) core

—A core version of the MPC603e microprocessor

—System core microprocessor supporting frequencies of 266-400 MHz—Separate 16-Kbyte data and instruction caches:–Four-way set associative–Physically addressed

–LRU replacement algorithm

—PowerPC architecture-compliant memory management unit (MMU)—Common on-chip processor (COP) test interface—Supports bus snooping for cache coherency

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Overview

•••

•

—Floating-point unit (FPU) supports floating-point arithmetic—Support for cache lockingLow-power consumption

Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)

Separate PLLs for G2_LE core and for the communications processor module (CPM)

—G2_LE core and CPM can run at different frequencies for power/performance optimization—Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1, 7:1, and 8:1 ratios

—Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ,and 8:1 ratios

-bit data and 32-bit address 60x bus

—Bus supports multiple master designs—up to two external masters—Supports single transfers and burst transfers

—-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller60x-to-PCI bridge

—Programmable host bridge and agent—32-bit data bus, 66 MHz, 3.3 V

—Synchronous and asynchronous 60x and PCI clock modes—All internal address space available to external PCI host—DMA for memory block transfers—PCI-to-60x address remappingSystem interface unit (SIU)—Clock synthesizer—Reset controller

—Real-time clock (RTC) register—Periodic interrupt timer

—Hardware bus monitor and software watchdog timer—IEEE 1149.1 JTAG test access portEight bank memory controller

—Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other user-definable peripherals—Byte write enables

—32-bit address decodes with programmable bank size

—Three user programmable machines, general-purpose chip-select machine, and page mode pipeline SDRAM machine

—Byte selects for -bit bus width (60x) —Dedicated interface logic for SDRAMDisable CPU mode

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Overview

•

Integrated security engine (SEC) (MPC8272 and MPC8248 only)

—Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms in hardware

Communications processor module (CPM)

—Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications peripherals

—Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port RAM size is 16 Kbyte plus 4Kbyte dedicated instruction RAM.)Universal serial bus (USB) controller

—Supports USB 2.0 full/low rate compatible—USB host mode

–Supports control, bulk, interrupt, and isochronous data transfers–CRC16 generation and checking

–NRZI encoding/decoding with bit stuffing

–Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub.–Flexible data buffers with multiple buffers per frame

–Supports local loopback mode for diagnostics (12 Mbps only)—Supports USB slave mode

–Four independent endpoints support control, bulk, interrupt, and isochronous data transfers–CRC16 generation and checking–CRC5 checking

–NRZI encoding/decoding with bit stuffing–12- or 1.5-Mbps data rate

–Flexible data buffers with multiple buffers per frame–Automatic retransmission upon transmit error

—Serial DMA channels for receive and transmit on all serial channels—Parallel I/O registers with open-drain and interrupt capability

—Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers—Two fast communication controllers (FCCs) supporting the following protocols:

–10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII)–Transparent

–HDLC—up to T3 rates (clear channel)

–One of the FCCs supports ATM (MPC8272 and MPC8271 only)—full-duplex SAR at 155 Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to -K external connections

—Three serial communications controllers (SCCs) identical to those on the MPC860 supporting the digital portions of the following protocols:

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Overview

•

Ethernet/IEEE 802.3 CDMA/CSHDLC/SDLC and HDLC bus

Universal asynchronous receiver transmitter (UART)Synchronous UART

Binary synchronous (BiSync) communicationsTransparent

QUICC multichannel controller (QMC) up to channels

•Independent transmit and receive routing, frame synchronization.

•Serial-multiplexed (full-duplex) input/output 2048-, 1544-, and 1536-Kbps PCM

highways

•Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN

basic rate, ISDN primary rate, and user defined.•Subchanneling on each time slot.

•Independent transmit and receive routing, frame synchronization and clocking

•Concatenation of any not necessarily consecutive time slots to channels independently

for Rx/Tx

•Supports H1,H11, and H12 channels•Allows dynamic allocation of channels

–SCC3 in NMSI mode is not usable when USB is enabled.

—Two serial management controllers (SMCs), identical to those of the MPC860

–Provides management for BRI devices as general-circuit interface (GCI) controllers in time-division-multiplexed (TDM) channels–Transparent

–UART (low-speed operation)

—One serial peripheral interface identical to the MPC860 SPI—One I2C controller (identical to the MPC860 I2C controller)–Microwire compatible

–Multiple-master, single-master, and slave modes—Up to two TDM interfaces

–Supports one group of two TDM channels –1024 bytes of SI RAM

—Eight independent baud rate generators and 14 input clock pins for supplying clocks to FCC, SCC, SMC, and USB serial channels

—Four independent 16-bit timers that can be interconnected as two 32-bit timersPCI bridge

—PCI Specification revision 2.2-compliant and supports frequencies up to 66 MHz—On-chip arbitration

—Support for PCI to 60x memory and 60x memory to PCI streaming—PCI host bridge or peripheral capabilities

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Operating Conditions

—Includes four DMA channels for the following transfers:–PCI-to-60x to 60x-to-PCI –60x-to-PCI to PCI-to-60x–PCI-to-60x to PCI-to-60x–60x-to-PCI to 60x-to-PCI

—Includes the configuration registers required by the PCI standard (which are automatically loaded from the EPROM to configure the MPC8272) and message and doorbell registers—Supports the I2O standard

—Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998)

—Support for 66-MHz, 3.3-V specification

—60x-PCI bus core logic, which uses a buffer pool to allocate buffers for each port

2Operating Conditions

Table3. Absolute Maximum Ratings 1

Rating

Core supply voltage 2PLL supply voltage2I/O supply voltage 3Input voltage 4

Junction temperature Storage temperature range

SymbolVDDVCCSYNVDDHVINTjTSTG

Value–0.3 – 2.25–0.3 – 2.25–0.3 – 4.0GND(–0.3) – 3.6

120(–55) – (+150)

UnitVVVV°C°C

Table3 shows the maximum electrical ratings.

4) at the maximums is not

guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.

2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V during normal operation. It is recommended that VDD/VCCSYN should be raised before or simultaneous with VDDH during power-on reset. VDD/VCCSYN may exceed VDDH by more than 0.4 V during power-on reset for no more than 100 ms.

3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than 2.5V during normal operation.

4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.

1 Absolute maximum ratings are stress ratings only; functional operation (see Table

Table4 lists recommended operational voltage conditions.

Table4. Recommended Operating Conditions 1

Rating

Core supply voltagePLL supply voltageI/O supply voltage

SymbolVDDVCCSYNVDDH

Value1.425 – 1.5751.425 – 1.5753.135 – 3.465

UnitVVV

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Operating Conditions

Table4. Recommended Operating Conditions 1 (continued)

Rating

Input voltage

Junction temperature (maximum)Ambient temperatureis not guaranteed.

2 Note that for extended temperature parts the range is (-40)

TA– 105Tj.

SymbolVINTjTA

Value

GND (–0.3) – 3.465

105 20–702

UnitV°C°C

1 Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC).

Figure2 shows the undershoot and overshoot voltage of the 60x bus memory interface of the MPC8272. Note that in PCI mode the I/O interface is different.

4 V

GVDD + 5%

GVDD

VIH

VIL

GND

GND – 0.3 VGND – 1.0 V

Not to exceed 10%of tSDRAM_CLK

Figure2. Overshoot/Undershoot Voltage

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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DC Electrical Characteristics

3DC Electrical Characteristics

Table5. DC Electrical Characteristics 1

Characteristic

SymbolVIHVILVIHCVILCIINIOZILIHVOH

Min2.0GND2.4GND————2.4

Max3.4650.83.4650.4101011—

UnitVVVVµAµAµAµAV

Table5 shows DC electrical characteristics.

Input high voltage—all inputs except TCK, TRST and PORESET 2Input low voltage 3CLKIN input high voltageCLKIN input low voltage

Input leakage current, VIN = VDDH 4Hi-Z (off state) leakage current, VIN = VDDH4Signal low input current, VIL = 0.8 VSignal high input current, VIH = 2.0 VOutput high voltage, IOH = –2 mA

except UTOPIA mode, and open drain pins

In UTOPIA mode 5 (UTOPIA pins only): IOH = -8.0mA PA[8–31]PB[18–31]PC[0–1,4–29]PD[7–25, 29–31]

In UTOPIA mode5 (UTOPIA pins only): IOL = 8.0mA PA[8–31]PB[18–31]PC[0–1,4–29]PD[7–25, 29–31]

VOL

—0.5V

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DC Electrical Characteristics

Table5. DC Electrical Characteristics 1 (continued)

Characteristic

IOL = 6.0mABRBG/IRQ6ABB/IRQ2TSA[0-31]TT[0-4]TBSTTSIZE[0–3]AACKARTRYDBG/IRQ7DBB/IRQ3D[0-63]

IRQ3/CKSTP_OUT/EXT_BR3IRQ4/CORE_SRESET/EXT_BG3IRQ5/TBEN/EXT_DBG3/CINTPSDVALTATEAGBL/IRQ1CI/BADDR29/IRQ2WT/BADDR30/IRQ3BADDR31/IRQ5/CINTCPU_BR/INT_OUTIRQ0/NMI_OUTPORESET/PCI_RSTHRESETSRESETRSTCONFSymbolVOL

Min—

Max0.4

UnitV

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DC Electrical Characteristics

Table5. DC Electrical Characteristics 1 (continued)

Characteristic

IOL = 5.3mACS[0-5]CS6/BCTL1/SMICS7/TLBSYNCBADDR27/ IRQ1BADDR28/ IRQ2ALE/ IRQ4BCTL0PWE[0–7]/PSDDQM[0–7]/PBS[0–7]PSDA10/PGPL0PSDWE/PGPL1POE/PSDRAS/PGPL2PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4PSDAMUX/PGPL5

PCI_CFG0 (PCI_HOST_EN)PCI_CFG1 (PCI_ARB_EN)PCI_CFG2 (DLL_ENABLE)MODCK1/RSRV/TC(0)/BNKSEL(0)MODCK2/CSE0/TC(1)/BNKSEL(1)MODCK3/CSE1/TC(2)/BNKSEL(2)IOL = 3.2mAPCI_PARPCI_FRAMEPCI_TRDYPCI_IRDYPCI_STOPPCI_DEVSELPCI_IDSELPCI_PERRPCI_SERRPCI_REQ0PCI_REQ1/ CPI_HS_ESPCI_GNT0PCI_GNT1/ CPI_HS_LESPCI_GNT2/ CPI_HS_ENUMPCI_RSTPCI_INTAPCI_REQ2DLLOUT

PCI_AD(0-31)

PCI_C(0–3)/BE(0-3)PA[8–31]PB[18–31]PC[0–1,4–29]PD[7–25, 29–31]TDO

SymbolVOL

Min—

Max0.4

UnitV

The default configuration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input. To prevent excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs.2

TCK, TRST and PORESET have min VIH = 2.5V3 V for IIC interface does not match IIC standard, but does meet IIC standard for V and should not cause any compatibility

ILOLissue.

4 The leakage current is measured for nominal VDDH,VCCSYN, and VDD.

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Thermal Characteristics

MPC8272 and MPC8271 only.

4Thermal Characteristics

Table6 describes thermal characteristics. Refer to Table2 for information on a given device’s package. Discussions of each characteristic are provided in sections 4.1 through 4.7. For the these discussions, PD=(VDD × IDD) + PI/O, where PI/O is the power dissipation of the I/O drivers.

Table6. Thermal Characteristics

Characteristic

Junction-to-ambient—single-layer board 1Junction-to-ambient—four-layer boardJunction-to-board 2Junction-to-case 3

Junction-to-package top 4

1 2

SymbolValue27

Unit°C/W

Air FlowNatural convection

1 m/sNatural convection

RθJA

2119

RθJARθJBRθJCRθJT

161182

°C/W°C/W°C/W°C/W

1 m/s———

Assumes no thermal vias

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.3

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).4

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

4.1Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, TJ, in 󰀀C can be obtained from the equation:

TJ = TA + (RθJA × PD)where:

TA = ambient temperature (ºC)

RθJA = package junction-to-ambient thermal resistance (ºC/W)PD = power dissipation in package

The junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible.

4.2Estimation with Junction-to-Case Thermal Resistance

Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:

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Thermal Characteristics

RθJA = RθJC + RθCA

where:

RθJA = junction-to-ambient thermal resistance (ºC/W)RθJC = junction-to-case thermal resistance (ºC/W)RθCA = case-to-ambient thermal resistance (ºC/W)

RθJC is device related and cannot be influenced by the user. The user adjusts the thermal environment to affect the case-to-ambient thermal resistance, RθCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required.

4.3Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance

describes the thermal performance when most of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages, especially PBGA packages, is strongly dependent on the board temperature.

If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation:

TJ = TB + (RθJB × PD)where:

RθJB = junction-to-board thermal resistance (ºC/W)TB = board temperature (ºC)

PD = power dissipation in package

If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and by attaching the thermal balls to the ground plane.

4.4Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application, or a more accurate and complex model of the package can be used in the thermal simulation.

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Thermal Characteristics

4.5Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation:

TJ = TT + (ΨJT × PD)where:

ΨJT = thermal characterization parameter

TT = thermocouple temperature on top of packagePD = power dissipation in package

The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40gauge typeT thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the case to avoid measurement errors caused by cooling effects of the thermocouple wire.

4.6Layout Practices

Each VDD and VDDH pin should be provided with a low-impedance path to the board’s power supplies. Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VDD and VDDH power supplies should be bypassed to ground using by-pass capacitors located as close as possible to the four sides of the package. For filtering high frequency noise, a capacitor of 0.1uF on each VDD and VDDH pin is recommended. Further, for medium frequency noise, a total of 2 capacitors of 47uF for VDD and 2 capacitors of 47uF for VDDH are also recommnded. The capacitor leads and associated printed circuit traces connecting to chip VDD, VDDH and ground should be kept to less than half an inch per capacitor lead. Boards should employ separate inner layers for power and GND planes.

All output pins on the MPC8272 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized to minimize overdamped conditions and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.

4.7References

(415) 9-5111

Semiconductor Equipment and Materials International805 East Middlefield Rd.Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) Specifications(Available from Global Engineering Documents)

800-854-7179 or 303-397-7956

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Power Dissipation

JEDEC Specifications http://www.jedec.org

1.C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.2.B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.

5Power Dissipation

Table7 provides preliminary, estimated power dissipation for various configurations. Note that suitable thermal management is required to ensure the junction temperature does not exceed the maximum

specified value. Also note that the I/O power should be included when determining whether to use a heat sink. For a complete list of possible clock configurations, refer to Section7, “Clock Configuration Modes.”

Table7. Estimated Power Dissipation for Various Configurations 1

CPM

Multiplication

Factor

3222

CPU

Multiplication

Factor

4343

PINT(W) 2, 3

CPU (MHz)

Vddl 1.5 VoltsNominal

66.67100100133

1 Test temperature = 105° C2 P

3 Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:

INT = IDD x VDD Watts

Bus (MHz)CPM(MHz)

Maximum

1.21.31.51.8

200200200267

266300400400

11.11.31.5

66.7 MHz = 0.35 W (nominal), 0.4 W (maximum)83.3 MHz = 0.4 W (nominal), 0.5 W (maximum)100 MHz = 0.5 W (nominal), 0.6 W (maximum)133 MHz = 0.7 W (nominal), 0.8 W (maximum)

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AC Electrical Characteristics

6AC Electrical Characteristics

The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for 66.67-/83.33-/100-/133-MHz MPC8272 devices. Note that AC timings are based on a 50-pf load for MAX Delay and 10-pf load for MIN delay. Typical output buffer impedances are shown in Table8.

Table8. Output Buffer Impedances 1

Output Buffers

60x bus

Memory controllerParallel I/OPCI

±25% with process and temperature.

2 Impedance value is selected through SIUMCR[20,21]. Refer

Typical Impedance (Ω)

45 or 27 245 or 272

4527

1 These are typical values at 65° C. Impedance may vary by

to the MPC8280 PowerQUICC II Family Reference Manual.

6.1CPM AC Characteristics

Table9. AC Characteristics for CPM Outputs 1

Table9 lists CPM output characteristics.

Spec Number

Characteristic

Max

Min

Value (ns)

Maximum Delay 66 MHz68108111111

83 MHz5.58108111111

Minimum Delay 83 MHz0.52022.50.50.5

100 MHz0.52022.50.50.5

133 MHz0.52022.50.50.5

100 133 66 MHzMHzMHz5.58108111111

5.58108111111

0.52022.50.50.5

sp36asp37aFCC outputs—internal clock (NMSI)sp36bsp37bFCC outputs—external clock (NMSI)

sp38asp39aSCC/SMC/SPI/I2C outputs—internal clock (NMSI)sp38bsp39bSCC/SMC/SPI/I2C outputs—external clock (NMSI)sp40sp42

sp41sp43

TDM outputs/SITIMER/IDMA outputs

sp42asp43aPIO outputsmeasured at the pin.

1 Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

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AC Electrical Characteristics

Table10 lists CPM input characteristics.

NOTE: Rise/Fall Time on CPM Input Pins

It is recommended that the rise/fall time on CPM input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90% of VCC; fall time refers to transitions from 90% to 10% of VCC.

Table10. AC Characteristics for CPM Inputs 1

Spec Number

Characteristic

Setup

Hold

66MHz62.538

Value (ns)

Setup Hold83MHz62.538

100MHz62.538

133MHz62.538

66MHz02022.50.5

83MHz02022.50.5

100MHz02022.50.5

133MHz02022.50.5

sp16asp17aFCC inputs—internal clock (NMSI)sp16bsp17bFCC inputs—external clock (NMSI)

sp18asp19aSCC/SMC/SPI/I2C inputs—internal clock (NMSI)sp18bsp19bSCC/SMC/SPI/I2C inputs—external clock (NMSI)sp20sp22

sp21sp23

TDM inputs/SI

PIO/TIMER/IDMA inputs

1 Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

NOTE

Although the specifications generally reference the rising edge of the clock, the following AC timing diagrams also apply when the falling edge is the active edge.

Figure3 shows the FCC internal clock.

BRG_OUT

sp17asp16aFCC input signals

sp36a/sp37aFCC output signals

Note: When GFMR[TCI] = 0sp36a/sp37aFCC output signals

Note: When GFMR.[TCI] = 1Figure3. FCC Internal Clock Diagram

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AC Electrical Characteristics

Figure4 shows the FCC external clock.

Serial ClKin

sp17bsp16bFCC input signals

sp36b/sp37bFCC output signals

Note: When GFMR[TCI] = 0

sp36b/sp37bFCC output signals

Note: When GFMR[TCI] = 1Figure4. FCC External Clock Diagram

Figure5 shows the SCC/SMC/SPI/I2C external clock.

Serial CLKin

sp18bSCC/SMC/SPI/I2C input signals

(See note)

new CLKinsp19bsp38b/sp39bSCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SPI:

1.Input sampled on the rising edge and output driven on the rising edge.2.Input sampled on the rising edge and output driven on the falling edge.

3.Input sampled on the falling edge and output driven on the falling edge (shown).4.Input sampled on the falling edge and output driven on the rising edge.Note: There are two possible timing conditions for SCC/SMC/I2C:

1.Input sampled on the falling edge and output driven on the falling edge (shown).2.Input sampled on the falling edge and output driven on the rising edge.

Figure5. SCC/SMC/SPI/I2C External Clock Diagram

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AC Electrical Characteristics

Figure6 shows the SCC/SMC/SPI/I2C internal clock.

BRG_OUT

sp18aSCC/SMC/SPI/I2C input signals

(See note)

sp19asp38a/sp39aSCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SCC and SPI:

1.Input sampled on the rising edge and output driven on the rising edge (shown).2.Input sampled on the rising edge and output driven on the falling edge.3.Input sampled on the falling edge and output driven on the falling edge.4.Input sampled on the falling edge and output driven on the rising edge.

Figure6. SCC/SMC/SPI/I2C Internal Clock Diagram

Figure7 shows TDM input and output signals.

Serial CLKin

sp20TDM input signals

sp40/sp41TDM output signals

Note: There are four possible TDM timing conditions:

sp21Figure7. TDM Signal Diagram

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AC Electrical Characteristics

Figure8 shows PIO and timer signals.

Sys clk

sp23sp22PIO/IDMA/TIMER[TGATE assertion] input signals

(See note)

sp23sp22TIMER input signal [TGATE deassertion]

(See note)

sp42/sp43IDMA output signals

sp42/sp43sp42a/sp43aTIMER(sp42/43)/ PIO(sp42a/sp43a)

output signals

Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.

Figure8. PIO and Timer Signal Diagram

6.2SIU AC Characteristics

NOTE: CLKIN Jitter and Duty Cycle

The CLKIN input to the MPC8272 should not exceed +/– 150 psec. This represents total input jitter—the combination of short term (peak-to-peak) and long term (cumulative). The duty cycle of CLKIN should not exceed the ratio of 40:60.

NOTE: Spread Spectrum Clocking

Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 60 KHz modulation rate regardless of input frequency.NOTE: PCI AC Timing

The MPC8272 meets the timing requirements of PCI Specification Revision 2.2. Refer to Section7, “Clock Configuration Modes,” and “Note: Tval (Output Hold)” to determine if a specific clock configuration is compliant.

Table11 lists SIU input characteristics.

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AC Electrical Characteristics

NOTE: Conditions

The following conditions must be met in order to operate the MPC8272 family devices with 133 MHz bus: single PowerQUICC II Bus mode must be used (no external master, BCR[EBM]=0); data bus must be in Pipeline mode (BRx[DR]=1); internal arbiter and memory controller must be used. For expected load of above 40 pF, it is recommended that data and address buses be configured to low (25 Ω) impedance (SIUMCR[HLBE0]=1, SIUMCR[HLBE1]=1).

Table11. AC Characteristics for SIU Inputs 1

Spec Number

Characteristic

Setup

Hold

66MHz

Value (ns)

Setup Hold83MHz5444

100MHz3.53.52.53.5

133MHzN/AN/A1.5N/A

66MHz0.50.5N/A0.5

83MHz0.50.50.50.5

100MHz0.50.50.50.5

133MHzN/AN/A0.5N/A

sp11sp12sp13sp15

sp10AACK/TA/TS/DBG/BG/BR/ARTRY/TEA 6sp10Data bus in normal mode

sp10Data bus in pipeline mode (without ECC and

PARITY)sp10All other pins

5N/A5

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.

Table12 lists SIU output characteristics.

Table12. AC Characteristics for SIU Outputs 1

Spec Number

Characteristic

Max

Min

66MHz

Maximum Delay 83MHz66.56.55.55.5

100MHz5.55.55.55.55.5

133MHzN/A4.5 24.54.5N/A

66MHz110.811

Value (ns)

Minimum Delay 83MHz110.811

100MHz110.811

133MHzN/A1 211N/A

sp31sp32sp33sp34sp35

sp30 PSDVAL/TEA/TA 7sp30

ADD/ADD_atr./BADDR/CI/GBL/WT

86.566

sp30 Data bus 3sp30sp30

Memory controller signals/ALEAll other signals

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

2 Value is for ADD only; other sp32/sp30 signals are not applicable.

3 To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.

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AC Electrical Characteristics

NOTE

Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing.

Figure9 shows the interaction of several bus signals.

CLKin

sp11AACK/TA/TS/DBG/BG/BR input signalssp11aARTRY/TEA input signalssp12DATA bus normal mode

input signal

sp15All other input signals

sp31PSDVAL/TEA/TA output signalssp32ADD/ADD_atr/BADDR/CI/GBL/WT output signals

sp30sp10sp10sp10sp10sp30sp33sp30DATA bus output signals

sp35sp30All other output signals

(except AP)

sp13DATA bus pipeline mode

input signal

sp10Figure9. Bus Signals

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AC Electrical Characteristics

Figure10 shows signal behavior in MEMC mode.

CLKin

V_CLK

Memory controller signalssp34/sp30Figure10. MEMC Mode Diagram

NOTE

Generally, all MPC8272 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals,

however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio selected, as shown in Table13.

Table13. Tick Spacing for Memory Controller Signals

Tick Spacing (T1 Occurs at the Rising Edge of CLKin)

PLL Clock Ratio

1:2, 1:3, 1:4, 1:5, 1:6

1:2.51:3.5

1/4 CLKin3/10 CLKin4/14 CLKin

1/2 CLKin1/2 CLKin1/2 CLKin

3/4 CLKin8/10 CLKin11/14 CLKin

Figure11 is a representation of the information in Table13.

CLKin

for 1:2, 1:3, 1:4, 1:5, 1:6

CLKin

for 1:2.5

CLKin

for 1:3.5

Figure11. Internal Tick Spacing for Memory Controller Signals

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AC Electrical Characteristics

NOTE

The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin’s rising edge.

6.3JTAG Timings

Table14. JTAG Timings1

Parameter

JTAG external clock frequency of operationJTAG external clock cycle time

JTAG external clock pulse width measured at 1.4VJTAG external clock rise and fall timesTRST assert timeInput setup times

Boundary-scan data

TMS, TDI

Input hold times

Boundary-scan data

TMS, TDI

Output valid times

Boundary-scan data

TDO

Output hold times

Boundary-scan data

TDO

tJTKLDXtJTKLOX

——

nsns

tJTKLDVtJTKLOV

——

1010

nsns

tJTDXKHtJTIXKH

1010

——

nsns

tJTDVKHtJTIVKH

——

nsns

Symbol2fJTGtJTGtJTKHKLtJTGR and tJTGFtTRST

Min03015025

Max33.3——5—

UnitMHznsnsnsns

Notes———

6Table14 lists the JTAG timings.

47,

4, 7

4, 74, 7

5, 75. 7

5, 7

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Clock Configuration Modes

Table14. JTAG Timings1 (continued)

Parameter

JTAG external clock to output high impedance

Boundary-scan data

TDO

Symbol2tJTKLDZtJTKLOZ

Min11

Max1010

Unitnsns

Notes

5, 6

56,

34567

All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.Non-JTAG signal input timing with respect to tTCLK.Non-JTAG signal output timing with respect to tTCLK.Guaranteed by design.

Guaranteed by design and device characterization.

7Clock Configuration Modes

As shown in Table15, the clocking mode is set according to two sources:

•PCI_CFG[0]— An input signal. Also defined as “PCI_HOST_EN.” Refer to the Chapter 6, “External Signals,” and Chapter 9, “PCI Bridge,” in the MPC8272 PowerQUICC II™ Family Reference Manual.

•PCI_MODCK—Bit 27 in the Hard Reset Configuration Word. Refer to Chapter 5, “Reset,” in the MPC8272 PowerQUICC II™ Family Reference Manual.

Table15. MPC8272 Clocking Modes

Pins

PCI_CFG[0] 1

0011

1 PCI_HOST_EN2

PCI_MODCK

0101

PCI agent PCI host

50–6625–5050–6625–50

Table16Table17Table18Table19

Clocking ModePCI Clock Frequency Range (MHz)Reference

Determines PCI clock frequency range.

Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits during the power-on reset—three hardware configuration pins (MODCK[1–3]) and four bits from

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Clock Configuration Modes

hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected clock operation mode as described in the following sections.

NOTE

Clock configurations change only after PORESET is asserted.NOTE: Tval (Output Hold)

The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum Tval=1 ns when PCI_MODCK = 0. Therefore, designers should use clock configurations that fit this condition to achieve PCI-compliant AC timing.

7.1PCI Host Mode

Table16 and Table17 show configurations for PCI host mode. The frequency values listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. Note that in PCI host mode the input clock is the bus clock.

Table16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2

Mode 3MODCK_H-MODCK[1-3]

Bus Clock(MHz)Low

High

CPM

Multiplication Factor 4

CPM Clock(MHz)Low

High

CPU

Multiplication Factor 5

CPU Clock(MHz)Low

High

PCI Division Factor 6

PCI Clock(MHz)Low

High

Default Modes (MODCK_H=0000)

0000_0000000_0010000_0100000_0110000_1000000_101

60.050.060.060.060.050.0

66.766.780.080.080.066.766.766.7

222.52.52.533.53

120.0133.3100.0133.3150.0200.0150.0200.0150.0200.0150.0200.0150.0200.0150.0200.0

2.5333.5433.54

150.0166.7150.0200.0180.0240.0210.0280.0240.0320.0150.0200.0175.0233.3200.0266.6

22333333

60.050.050.050.050.050.050.050.0

66.766.7 66.766.766.766.766.766.7

0000_110 50.00000_111

50.0

Full Configuration Modes

0001_0000001_0010001_0100001_011

50.050.050.050.0

66.766.766.766.7

3333

150.0200.0150.0200.0150.0200.0150.0200.0

5678

250.0333.3300.0400.0350.0466.00.0533.3

3333

50.050.050.050.0

66.766.766.766.7

0010_0000010_001

50.050.0

66.766.7

200.0266.6200.0266.6

250.0333.3300.0400.0

50.050.0

66.766.7

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Clock Configuration Modes

Table16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]0010_0100010_011

Bus Clock(MHz)Low50.050.0

High66.766.7

CPM

Multiplication Factor 4

CPM Clock(MHz)Low

High

CPU

Multiplication Factor 5

CPU Clock(MHz)Low

High

PCI Division Factor 6

PCI Clock(MHz)Low50.050.0

High66.766.7

200.0266.6200.0266.6

350.0466.00.0533.3

0010_1000010_1010010_110

75.0100.075.0100.075.0100.0

444

300.0400.0300.0400.0300.0400.0

55.56

375.0500.0412.5549.9450.0599.9

666

50.050.050.0

66.766.766.7

0011_0000011_0010011_0100011_011

50.050.050.050.0

66.766.766.766.7

5555

250.0333.3250.0333.3250.0333.3250.0333.3

5678

250.0333.3300.0400.0350.0466.00.0533.3

5555

50.050.050.050.0

66.766.766.766.7

0100_0000100_0010100_0100100_011

50.050.050.0

66.766.766.7

666

300.0400.0300.0400.0300.0400.0

Reserved

678

300.0400.0350.0466.00.0533.3

666

50.050.050.0

66.766.766.7

0101_0000101_001

60.050.0

66.766.766.766.766.7

22222

120.0133.3100.0133.3100.0133.3100.0133.3100.0133.3

2.533.544.5

150.0166.7150.0200.0175.0233.3200.0266.6225.0300.0

22222

60.050.050.050.050.0

66.766.766.766.766.7

0101_010 50.00101_0110101_100

50.050.0

0101_1010101_1100101_111

83.3111.183.3111.183.3111.1

333

250.0333.3250.0333.3250.0333.3

3.544.5

291.7388.9333.3444.4375.0500.0

555

50.050.050.0

66.766.766.7

0110_0000110_0010110_010

60.060.060.0

80.080.080.0

2.52.52.5

150.0200.0150.0200.0150.0200.0

2.533.5

150.0200.0180.0240.0210.0280.0

333

50.050.050.0

66.766.766.7

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Clock Configuration Modes

Table16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]0110_0110110_1000110_1010110_110

Bus Clock(MHz)Low60.060.060.060.0

High80.080.080.080.0

CPM

Multiplication Factor 4

2.52.52.52.5

CPM Clock(MHz)Low

High

CPU

Multiplication Factor 5

44.556

CPU Clock(MHz)Low

High

PCI Division Factor 6

3333

PCI Clock(MHz)Low50.050.050.050.0

High66.766.766.766.7

150.0200.0150.0200.0150.0200.0150.0200.0

240.0320.0270.0360.0300.0400.0360.0480.0

0111_0000111_001

50.0

66.766.766.766.7

3333

150.0200.0150.0200.0150.0200.0150.0200.0

Reserved

33.544.5

150.0200.0175.0233.3200.0266.6225.0300.0

3333

50.050.050.050.0

66.766.766.766.7

0111_010 50.00111_0110111_100

50.050.0

1000_0001000_0011000_0101000_0111000_1001000_1011000_110

66.766.766.766.766.766.7

88.988.988.988.988.988.9

333333

200.0266.6200.0266.6200.0266.6200.0266.6200.0266.6200.0266.6

Reserved

33.544.566.5

200.0266.6233.3311.1266.7355.5300.0400.0400.0533.3433.3577.7

444444

50.050.050.050.050.050.0

66.766.766.766.766.766.7

1001_0001001_0011001_0101001_0111001_100

57.157.157.1

76.276.276.2

3.53.53.5

200.0266.6200.0266.6200.0266.6

ReservedReserved

3.544.5

200.0266.6228.6304.7257.1342.8

444

50.050.050.0

66.766.766.7

1001_1011001_1101001_111

85.7114.385.7114.385.7114.3

3.53.53.5

300.0400.0300.0400.0300.0400.0

55.56

428.6571.4471.4628.5514.3685.6

666

50.050.050.0

66.766.766.7

1010_00075.0100.02150.0200.02150.0200.0350.066.7

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Clock Configuration Modes

Table16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]1010_0011010_0101010_0111010_100

Bus Clock(MHz)Low

High

CPM

Multiplication Factor 4

2222

CPM Clock(MHz)Low

High

CPU

Multiplication Factor 5

2.533.54

CPU Clock(MHz)Low

High

PCI Division Factor 6

3333

PCI Clock(MHz)Low50.050.050.050.0

High66.766.766.766.7

75.0100.075.0100.075.0100.075.0100.0

150.0200.0150.0200.0150.0200.0150.0200.0

187.5250.0225.0300.0262.5350.0300.0400.0

1010_1011010_1101010_111

100.0133.3100.0133.3100.0133.3

222

200.0266.6200.0266.6200.0266.6

2.533.5

250.0333.3300.0400.0350.0466.6

444

50.050.050.0

66.766.766.7

1011_0001011_0011011_0101011_0111011_1001011_101

80.0106.780.0106.780.0106.780.0106.780.0106.7

2.52.52.52.52.5

200.0266.6200.0266.6200.0266.6200.0266.6200.0266.6

Reserved

2.533.544.5

200.0266.6240.0320.0280.0373.3320.0426.6360.0480.0

44444

50.050.050.050.050.0

66.766.766.766.766.7

1101_000 100.0133.31101_001 100.0133.31101_010

100.0133.3

2.52.52.52.52.5

250.0333.3250.0333.3250.0333.3250.0333.3250.0333.3

33.544.55

300.0400.0350.0466.00.0533.3450.0599.9500.0666.6

55555

50.050.050.050.050.0

66.766.766.766.766.7

1101_011 100.0133.31101_100 100.0133.3

1101_101 125.0166.71101_110 125.0166.7

250.0333.3250.0333.3

375.0500.0500.0666.6

50.050.0

66.766.7

1110_0001110_0011110_0101110_0111110_100

100.0133.3100.0133.3100.0133.3100.0133.3100.0133.3

33333

300.0400.0300.0400.0300.0400.0300.0400.0300.0400.0

3.544.555.5

350.0466.00.0533.3450.0599.9500.0666.6550.0733.3

66666

50.050.050.050.050.0

66.766.766.766.766.7

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Clock Configuration Modes

Table16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]

Bus Clock(MHz)Low

High

CPM

Multiplication Factor 4

CPM Clock(MHz)Low

High

CPU

Multiplication Factor 5

CPU Clock(MHz)Low

High

PCI Division Factor 6

PCI Clock(MHz)Low

High

1100_0001100_0011100_010

ReservedReservedReserved

1 The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a

23456

table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial

temperature devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz. PCI_MODCK determines the PCI clock frequency range. Refer to Table17 for lower range configurations.

MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins.

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 0, the ratio of CPM_CLK/PCI_CLK should be calculated from SCCR[PCIDF] as follows:

CPM_CLK/PCI_CLK = (PCIDF + 1) / 2.

Table17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2

Mode 3MODCK_H-MODCK[1-3]

Bus Clock(MHz)Low

High

CPM

Multiplication Factor 4

CPMClock(MHz)Low

High

CPU

Multiplication Factor 5

CPUClock(MHz)Low

High

PCI Division Factor 6

PCI Clock(MHz)Low

High

Default Modes (MODCK_H=0000)

0000_0000000_0010000_0100000_0110000_1000000_1010000_1100000_111

60.0100.050.0100.060.0120.060.0120.060.0120.050.0100.050.0100.050.0100.0

222.52.52.5333

120.0200.0100.0200.0150.0300.0150.0300.0150.0300.0150.0300.0150.0300.0150.0300.0

2.5333.5433.54

150.0250.0150.0300.0180.0360.0210.0420.0240.0480.0150.0300.0175.0350.0200.0400.0

44666666

30.025.025.025.025.025.025.025.0

50.050.050.050.050.050.050.050.0

Full Configuration Modes

0001_0000001_001

50.0100.050.0100.0

150.0300.0150.0300.0

250.0500.0300.0600.0

25.025.0

50.050.0

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

元器件交易网www.cecb2b.com

Clock Configuration Modes

Table17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]0001_0100001_011

Bus Clock(MHz)Low

High

CPM

Multiplication Factor 4

CPMClock(MHz)Low

High

CPU

Multiplication Factor 5

CPUClock(MHz)Low

High

PCI Division Factor 6

PCI Clock(MHz)Low25.025.0

High50.050.0

50.0100.050.0100.0

150.0300.0150.0300.0

350.0700.0400.0800.0

0010_0000010_0010010_0100010_011

50.0100.050.0100.050.0100.050.0100.0

4444

200.0400.0200.0400.0200.0400.0200.0400.0

5678

250.0500.0300.0600.0350.0700.0400.0800.0

8888

25.025.025.025.0

50.050.050.050.0

0010_1000010_1010010_110

37.537.537.5

75.075.075.0

444

150.0300.0150.0300.0150.0300.0

55.56

187.5375.0206.3412.5225.0450.0

666

25.025.025.0

50.050.050.0

0011_0000011_0010011_0100011_011

30.025.025.025.0

50.050.050.050.0

5555

150.0250.0125.0250.0125.0250.0125.0250.0

5678

150.0250.0150.0300.0175.0350.0200.0400.0

5555

30.025.025.025.0

50.050.050.050.0

0100_0000100_0010100_0100100_011

25.025.025.0

50.050.050.0

666

150.0300.0150.0300.0150.0300.0

Reserved

678

150.0300.0175.0350.0200.0400.0

666

25.025.025.0

50.050.050.0

0101_0000101_0010101_0100101_0110101_100

60.0100.050.0100.050.0100.050.0100.050.0100.0

22222

120.0200.0100.0200.0100.0200.0100.0200.0100.0200.0

2.533.544.5

150.0250.0150.0300.0175.0350.0200.0400.0225.0450.0

44444

30.025.025.025.025.0

50.050.050.050.050.0

0101_1010101_110

42.941.7

83.383.3

128.6250.0125.0250.0

3.54

150.0291.7166.7333.3

25.725.0

50.050.0

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

Table17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]0101_111

Bus Clock(MHz)Low41.7

High83.3

CPM

Multiplication Factor 4

CPMClock(MHz)Low

High

CPU

Multiplication Factor 5

4.5

CPUClock(MHz)Low

High

PCI Division Factor 6

PCI Clock(MHz)Low25.0

High50.0

125.0250.0187.5375.0

0110_0000110_0010110_0100110_0110110_1000110_1010110_110

60.0120.060.0120.060.0120.060.0120.060.0120.060.0120.060.0120.0

2.52.52.52.52.52.52.5

150.0300.0150.0300.0150.0300.0150.0300.0150.0300.0150.0300.0150.0300.0

2.533.544.556

150.0300.0180.0360.0210.0420.0240.0480.0270.0540.0300.0600.0360.0720.0

6666666

25.025.025.025.025.025.025.0

50.050.050.050.050.050.050.0

0111_0000111_0010111_0100111_0110111_100

50.0100.050.0100.050.0100.050.0100.0

3333

150.0300.0150.0300.0150.0300.0150.0300.0

Reserved

33.544.5

150.0300.0175.0350.0200.0400.0225.0450.0

6666

25.025.025.025.0

50.050.050.050.0

1000_0001000_0011000_0101000_0111000_1001000_1011000_110

66.7133.366.7133.366.7133.366.7133.366.7133.366.7133.3

333333

200.0400.0200.0400.0200.0400.0200.0400.0200.0400.0200.0400.0

Reserved

33.544.566.5

200.0400.0233.3466.7266.7533.3300.0600.0400.0800.0433.3866.7

888888

25.025.025.025.025.025.0

50.050.050.050.050.050.0

1001_0001001_0011001_0101001_0111001_1001001_101

57.1114.357.1114.357.1114.342.9

85.7

3.53.53.53.5

200.0400.0200.0400.0200.0400.0150.0300.0

ReservedReserved

3.544.55

200.0400.0228.57.1257.1514.3214.3428.6

8886

25.025.025.025.0

50.050.050.050.0

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

Table17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]1001_1101001_111

Bus Clock(MHz)Low42.942.9

High85.785.7

CPM

Multiplication Factor 4

3.53.5

CPMClock(MHz)Low

High

CPU

Multiplication Factor 5

5.56

CPUClock(MHz)Low

High

PCI Division Factor 6

PCI Clock(MHz)Low25.025.0

High50.050.0

150.0300.0150.0300.0

235.7471.4257.1514.3

1010_0001010_0011010_0101010_0111010_100

75.0150.075.0150.075.0150.075.0150.075.0150.0

22222

150.0300.0150.0300.0150.0300.0150.0300.0150.0300.0

22.533.54

150.0300.0187.5375.0225.0450.0262.5525.0300.0600.0

66666

25.025.025.025.025.0

50.050.050.050.050.0

1010_1011010_1101010_111

100.0200.0100.0200.0100.0200.0

222

200.0400.0200.0400.0200.0400.0

2.533.5

250.0500.0300.0600.0350.0700.0

888

25.025.025.0

50.050.050.0

1011_0001011_0011011_0101011_0111011_1001011_101

80.0160.080.0160.080.0160.080.0160.080.0160.0

2.52.52.52.52.5

200.0400.0200.0400.0200.0400.0200.0400.0200.0400.0

Reserved

2.533.544.5

200.0400.0240.0480.0280.0560.0320.00.0360.0720.0

88888

25.025.025.025.025.0

50.050.050.050.050.0

1101_0001101_0011101_0101101_0111101_100

50.0100.050.0100.050.0100.050.0100.050.0100.0

2.52.52.52.52.5

125.0250.0125.0250.0125.0250.0125.0250.0125.0250.0

33.544.55

150.0300.0175.0350.0200.0400.0225.0450.0250.0500.0

55555

25.025.025.025.025.0

50.050.050.050.050.0

1101_1011101_110

62.5125.062.5125.0

125.0250.0125.0250.0

187.5375.0250.0500.0

25.025.0

50.050.0

1110_00050.0100.03150.0300.03.5175.0350.0625.050.0

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

元器件交易网www.cecb2b.com

Clock Configuration Modes

Table17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]1110_0011110_0101110_0111110_100

Bus Clock(MHz)Low

High

CPM

Multiplication Factor 4

3333

CPMClock(MHz)Low

High

CPU

Multiplication Factor 5

44.555.5

CPUClock(MHz)Low

High

PCI Division Factor 6

6666

PCI Clock(MHz)Low25.025.025.025.0

High50.050.050.050.0

50.0100.050.0100.050.0100.050.0100.0

150.0300.0150.0300.0150.0300.0150.0300.0

200.0400.0225.0450.0250.0500.0275.0550.0

1100_0001100_0011100_010

ReservedReservedReserved

1 The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a

23456

temperature devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz. PCI_MODCK determines the PCI clock frequency range. Refer to Table16 for higher range configurations.

MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins.

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 1, the ratio of CPM_CLK/PCI_CLK should be calculated from PCIDF as follows:

PCIDF = 3 > CPM_CLK/PCI_CLK = 4PCIDF = 5 > CPM_CLK/PCI_CLK = 6PCIDF = 7 > CPM_CLK/PCI_CLK = 8PCIDF = 9 > CPM_CLK/PCI_CLK = 5PCIDF = B > CPM_CLK/PCI_CLK = 6

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

7.2PCI Agent Mode

Table18 and Table19 show configurations for PCI agent mode. The frequency values listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting

configuration does not exceed the frequency rating of the user’s device. Note that in PCI agent mode the input clock is PCI clock.

Table18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2

Mode 3MODCK_H-MODCK[1-3]

PCI Clock(MHz)Low

High

CPM

MultiplicationFactor 4

CPMClock(MHz)Low

High

CPU

MultiplicationFactor 5

CPUClock(MHz)Low

High

BusDivisionFactor

Bus Clock(MHz)Low

High

Default Modes (MODCK_H=0000)

0000_0000000_0010000_0100000_0110000_1000000_1010000_1100000_111

60.050.050.050.050.050.050.050.0

66.766.766.766.766.766.766.766.7

22333344

120.0133.3100.0133.3150.0200.0150.0200.0150.0200.0150.0200.0200.0266.6200.0266.6

2.533433.53.53

150.0166.7150.0200.0150.0200.0200.0266.6180.0240.0210.0280.0233.3311.1240.0320.0

22332.52.532.5

60.050.050.050.060.060.066.7

66.766.766.766.780.080.088.9

80.0106.7

Full Configuration Modes

0001_0010001_0100001_0110001_100

60.050.050.050.0

66.766.766.766.7

2222

120.0133.3100.0133.3100.0133.3100.0133.3

5678

150.0166.7150.0200.0175.0233.3200.0266.6

4444

30.025.025.025.0

33.333.333.333.3

0010_0010010_0100010_0110010_100

50.050.050.050.0

66.766.766.766.7

3333

150.0200.0150.0200.0150.0200.0150.0200.0

33.544.5

180.0240.0210.0280.0240.0320.0270.0360.0

2.52.52.52.5

60.060.060.060.0

80.080.080.080.0

0011_0000011_0010011_0100011_0110011_100

ReservedReservedReservedReservedReserved

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

Table18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]

PCI Clock(MHz)Low

High

CPM

MultiplicationFactor 4

CPMClock(MHz)Low

High

CPU

MultiplicationFactor 5

CPUClock(MHz)Low

High

BusDivisionFactor

Bus Clock(MHz)Low

High

0100_0000100_0010100_0100100_0110100_100

50.050.050.050.0

66.766.766.766.7

3333

150.0200.0150.0200.0150.0200.0150.0200.0

Reserved

33.544.5

150.0200.0175.0200.0200.0266.6225.0300.0

3333

50.050.050.050.0

66.766.766.766.7

0101_0000101_0010101_0100101_0110101_1000101_1010101_110

50.050.050.050.050.050.050.0

66.766.766.766.766.766.766.7

5555555

250.0333.3250.0333.3250.0333.3250.0333.3250.0333.3250.0333.3250.0333.3

2.533.544.555.5

250.0333.3300.0400.0350.0466.00.0533.3450.0599.9500.0666.6550.0733.3

2.52.52.52.52.52.52.5

100.0133.3100.0133.3100.0133.3100.0133.3100.0133.3100.0133.3100.0133.3

0110_0000110_0010110_0100110_0110110_100

50.050.050.050.0

66.766.766.766.7

4444

200.0266.6200.0266.6200.0266.6200.0266.6

Reserved

33.544.5

200.0266.6233.3311.1266.7355.5300.0400.0

3333

66.766.766.766.7

88.988.988.988.9

0111_0000111_0010111_0100111_011

50.050.050.050.0

66.766.766.766.7

3333

150.0200.0150.0200.0150.0200.0150.0200.0

22.533.5

150.0200.0187.5250.0225.0300.0262.5350.0

2222

75.0100.075.0100.075.0100.075.0100.0

1000_0001000_0011000_0101000_011

50.050.050.0

66.766.766.7

333

150.0200.0150.0200.0150.0200.0

Reserved

2.533.5

150.0166.7180.0240.0210.0280.0

2.52.52.5

60.060.060.0

80.080.080.0

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

Table18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]1000_1001000_101

PCI Clock(MHz)Low50.050.0

High66.766.7

CPM

MultiplicationFactor 4

CPMClock(MHz)Low

High

CPU

MultiplicationFactor 5

44.5

CPUClock(MHz)Low

High

BusDivisionFactor2.52.5

Bus Clock(MHz)Low60.060.0

High80.080.0

150.0200.0150.0200.0

240.0320.0270.0360.0

1001_0001001_0011001_0101001_0111001_100

50.050.0

66.766.7

200.0266.6200.0266.6

ReservedReservedReserved

44.5

200.0266.6225.0300.0

50.050.0

66.766.7

1010_0001010_0011010_0101010_0111010_100

50.050.050.050.0

66.766.766.766.7

4444

200.0266.6200.0266.6200.0266.6200.0266.6

Reserved

33.544.5

200.0266.6233.3311.1266.7355.5300.0400.0

3333

66.766.766.766.7

88.988.988.988.9

1011_0001011_0011011_0101011_0111011_100

50.050.050.050.0

66.766.766.766.7

4444

200.0266.6200.0266.6200.0266.6200.0266.6

Reserved

2.533.54

200.0266.6240.0320.0280.0373.3320.0426.6

2.52.52.52.5

80.0106.780.0106.780.0106.780.0106.7

1011_1011011_1101011_111

50.050.050.0

66.766.766.7

444

200.0266.6200.0266.6200.0266.6

2.533.5

250.0333.3300.0400.0350.0466.6

222

100.0133.3100.0133.3100.0133.3

1100_1011100_1101100_1111101_000

50.050.050.050.0

66.766.766.766.7

6666

300.0400.0300.0400.0300.0400.0300.0400.0

44.555.5

400.0533.3450.0599.9500.0666.6550.0733.3

3333

100.0133.3100.0133.3100.0133.3100.0133.3

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

Table18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]1101_0011101_0101101_0111101_100

PCI Clock(MHz)Low50.050.050.050.0

High66.766.766.766.7

CPM

MultiplicationFactor 4

6666

CPMClock(MHz)Low

High

CPU

MultiplicationFactor 5

3.544.55

CPUClock(MHz)Low

High

BusDivisionFactor2.52.52.52.5

Bus Clock(MHz)Low

High

300.0400.0300.0400.0300.0400.0300.0400.0

420.0559.9480.0639.9540.0719.9600.0799.9

120.0160.0120.0160.0120.0160.0120.0160.0

1110_0001110_0011110_0101110_011

50.050.050.050.0

66.766.766.766.7

5555

250.0333.3250.0333.3250.0333.3250.0333.3

2.533.54

312.5416.6375.0500.0437.5583.3500.0666.6

2222

125.0166.7125.0166.7125.0166.7125.0166.7

1110_1001110_1011110_1101110_111

50.050.050.050.0

66.766.766.766.7

5555

250.0333.3250.0333.3250.0333.3250.0333.3

44.555.5

333.3444.4375.0500.0416.7555.5458.3611.1

3333

83.3111.183.3111.183.3111.183.3111.1

1100_0001100_0011100_010

ReservedReservedReserved

1 The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a

2345

temperature devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz. PCI_MODCK determines the PCI clock frequency range. Refer to Table19 for lower range configurations. MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins. CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

Table19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2

Mode 3MODCK_H-MODCK[1-3]

PCI Clock(MHz)Low

High

CPM

MultiplicationFactor 4

CPMClock(MHz)Low

High

CPU

MultiplicationFactor 5

CPUClock(MHz)Low

High

BusDivisionFactor

Bus Clock(MHz)Low

High

Default Modes (MODCK_H=0000)

0000_0000000_0010000_0100000_0110000_1000000_1010000_1100000_111

30.025.025.025.025.025.025.025.0

50.050.050.050.050.050.050.050.0

44666688

120.0200.0100.0200.0150.0300.0150.0300.0150.0300.0150.0300.0200.0400.0200.0400.0

2.533433.53.53

150.0250.0150.0300.0150.0300.0200.0400.0180.0360.0210.0420.0233.3466.7240.0480.0

22332.52.532.5

60.0100.050.0100.050.0100.050.0100.060.0120.060.0120.066.7133.380.0160.0

Full Configuration Modes

0001_0010001_0100001_0110001_100

30.025.025.025.0

50.050.050.050.0

4444

120.0200.0100.0200.0100.0200.0100.0200.0

5678

150.0250.0150.0300.0175.0350.0200.0400.0

4444

30.025.025.025.0

50.050.050.050.0

0010_0010010_0100010_0110010_100

25.025.025.025.0

50.050.050.050.0

6666

150.0300.0150.0300.0150.0300.0150.0300.0

33.544.5

180.0360.0210.0420.0240.0480.0270.0540.0

2.52.52.52.5

60.0120.060.0120.060.0120.060.0120.0

0011_0000011_0010011_0100011_0110011_100

37.532.128.125.0

50.050.050.050.0

4444

150.0200.0128.6200.0112.5200.0100.0200.0

Reserved

33.544.5

150.0200.0150.0233.3150.0266.7150.0300.0

3333

50.042.937.533.3

66.766.766.766.7

0100_0000100_0010100_0100100_011

25.025.025.0

50.050.050.0

666

150.0300.0150.0300.0150.0300.0

Reserved

33.54

150.0300.0175.0350.0200.0400.0

333

50.0100.050.0100.050.0100.0

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

Table19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]0100_100

PCI Clock(MHz)Low25.0

High50.0

CPM

MultiplicationFactor 4

CPMClock(MHz)Low

High

CPU

MultiplicationFactor 5

4.5

CPUClock(MHz)Low

High

BusDivisionFactor

Bus Clock(MHz)Low

High

150.0300.0225.0450.050.0100.0

0101_0000101_0010101_0100101_0110101_1000101_1010101_110

30.025.025.025.025.025.025.0

50.050.050.050.050.050.050.0

5555555

150.0250.0125.0250.0125.0250.0125.0250.0125.0250.0125.0250.0125.0250.0

2.533.544.555.5

150.0250.0150.0300.0175.0350.0200.0400.0225.0450.0250.0500.0275.0550.0

2.52.52.52.52.52.52.5

60.0100.050.0100.050.0100.050.0100.050.0100.050.0100.050.0100.0

0110_0000110_0010110_0100110_0110110_100

25.025.025.025.0

50.050.050.050.0

8888

200.0400.0200.0400.0200.0400.0200.0400.0

Reserved

33.544.5

200.0400.0233.3466.7266.7533.3300.0600.0

3333

66.7133.366.7133.366.7133.366.7133.3

0111_0000111_0010111_0100111_011

25.025.025.025.0

50.050.050.050.0

6666

150.0300.0150.0300.0150.0300.0150.0300.0

22.533.5

150.0300.0187.5375.0225.0450.0262.5525.0

2222

75.0150.075.0150.075.0150.075.0150.0

1000_0001000_0011000_0101000_0111000_1001000_101

25.025.025.025.025.0

50.050.050.050.050.0

66666

150.0300.0150.0300.0150.0300.0150.0300.0150.0300.0

Reserved

2.533.544.5

150.0300.0180.0360.0210.0420.0240.0480.0270.0540.0

2.52.52.52.52.5

60.0120.060.0120.060.0120.060.0120.060.0120.0

1001_0001001_001

ReservedReserved

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

Table19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]1001_0101001_0111001_100

25.025.0

50.050.0

200.0400.0200.0400.0

PCI Clock(MHz)Low

High

CPM

MultiplicationFactor 4

CPMClock(MHz)Low

High

CPU

MultiplicationFactor 5Reserved

44.5

200.0400.0225.0450.0

50.0100.050.0100.0

CPUClock(MHz)Low

High

BusDivisionFactor

Bus Clock(MHz)Low

High

1010_0001010_0011010_0101010_0111010_100

25.025.025.025.0

50.050.050.050.0

8888

200.0400.0200.0400.0200.0400.0200.0400.0

Reserved

33.544.5

200.0400.0233.3466.7266.7533.3300.0600.0

3333

66.7133.366.7133.366.7133.366.7133.3

1011_0001011_0011011_0101011_0111011_100

25.025.025.025.0

50.050.050.050.0

8888

200.0400.0200.0400.0200.0400.0200.0400.0

Reserved

2.533.54

200.0400.0240.0480.0280.0560.0320.00.0

2.52.52.52.5

80.0160.080.0160.080.0160.080.0160.0

1011_1011011_1101011_111

25.025.025.0

50.050.050.0

888

200.0400.0200.0400.0200.0400.0

2.533.5

250.0500.0300.0600.0350.0700.0

222

100.0200.0100.0200.0100.0200.0

1100_1011100_1101100_1111101_000

25.025.025.025.0

50.050.050.050.0

6666

150.0300.0150.0300.0150.0300.0150.0300.0

44.555.5

200.0400.0225.0450.0250.0500.0275.0550.0

3333

50.0100.050.0100.050.0100.050.0100.0

1101_0011101_0101101_0111101_100

25.025.025.025.0

50.050.050.050.0

6666

150.0300.0150.0300.0150.0300.0150.0300.0

3.544.55

210.0420.0240.0480.0270.0540.0300.0600.0

2.52.52.52.5

60.0120.060.0120.060.0120.060.0120.0

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Clock Configuration Modes

Table19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued)

Mode 3MODCK_H-MODCK[1-3]1110_0001110_0011110_0101110_011

PCI Clock(MHz)Low25.025.028.625.0

High50.050.050.050.0

CPM

MultiplicationFactor 4

5555

CPMClock(MHz)Low

High

CPU

MultiplicationFactor 5

2.533.54

CPUClock(MHz)Low

High

BusDivisionFactor

2222

Bus Clock(MHz)Low

High

125.0250.0125.0250.0142.9250.0125.0250.0

156.3312.5187.5375.0250.0437.5250.0500.0

62.5125.062.5125.071.4125.062.5125.0

1110_1001110_1011110_1101110_111

25.025.025.025.0

50.050.050.050.0

5555

125.0250.0125.0250.0125.0250.0125.0250.0

44.555.5

166.7333.3187.5375.0208.3416.7229.2458.3

3333

41.741.741.741.7

83.383.383.383.3

1100_0001100_0011100_010

ReservedReservedReserved

1 The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a

2345

temperature devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz. PCI_MODCK determines the PCI clock frequency range. Refer to Table18 for higher range configurations.

MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins.

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Pinout

8Pinout

The figure and table below show the pin assignments and pinout for the 516 PBGA package.Figure12 shows the pinout of the 516 PBGA package as viewed from the top surface.

1ABCDEFGHJKLMNPRTUVWYAAABACADAEAF

Not to Scale

2345671011121314151617181920212223242526

ABCDEFGHJKLMNPRTUVWYAAABACADAEAF

2345671011121314151617181920212223242526

Figure12. Pinout of the 516 PBGA Package (View from Top)

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Pinout

Table20 shows the pinout of the MPC8272. Note that the pins in the “MPC8272/8271 Only” column relate to Utopia functionality.

Table20. Pinout

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

BRBG/IRQ6ABB/IRQ2TSA0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24

Ball

MPC8272/MPC8271 Only

A19D2C1D1A3B5D8C6A4A6B6C7B7A7D9E11C9B9D11A9B10A10B11A11D12A12D13B13C13

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

A25A26A27A28A29A30A31TT0TT1TT2TT3TT4TBSTTSIZ0TSIZ1TSIZ2TSIZ3AACKARTRYDBG/IRQ7DBB/IRQ3D0D1D2D3D4D5D6D7D8D9

Ball

MPC8272/MPC8271 Only

C14B14D14E14A14B15A15B3E8D7C4E7E3E4E5C3D5D3C2F16D18AC1AA1V3R5P4M4J4G1W6Y3

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

D10D11D12D13D14D15D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31D32D33D34D35D36D37D38D39D40

Ball

MPC8272/MPC8271 Only

V1N6P3M2J5G3AB3Y1T4T3P2M1J1G4AB2W4V2T1N5L1H1G5W5W2T5T2N1K3H2F1AA2

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

D41D42D43D44D45D46D47D48D49D50D51D52D53D54D55D56D57D58D59D60D61D62D63

IRQ3/CKSTP_OUT/EXT_BR3IRQ4/CORE_SRESET/EXT_BG3IRQ5/TBEN/EXT_DBG3/CINTPSDVALTATEAGBL/IRQ1CI/BADDR29/IRQ2Ball

MPC8272/MPC8271 Only

W1U3R2N2L2H4F2AB1U4U1R3N3K2H5F4AA3U5U2P5M3K4H3E1B16C15Y4C19AA4AB6D15D16

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

Ball

MPC8272/MPC8271 Only

C16E17B20AE6AD7AF5AC8AF6AD8AC9AB9AB8AC7AF4AF3AD6AE5AE3AF2AC6AC5AD4AB5AE2AD3AB4AC3AD2AC2AD22AC21

WT/BADDR30/IRQ3BADDR31/IRQ5/CINTCPU_BR/INT_OUTCS0CS1CS2CS3CS4CS5CS6/BCTL1/SMICS7/TLBISYNCBADDR27/IRQ1BADDR28/IRQ2ALE/IRQ4BCTL0PWE0/PSDDQM0/PBS0PWE1/PSDDQM1/PBS1PWE2/PSDDQM2/PBS2PWE3/PSDDQM3/PBS3PWE4/PSDDQM4/PBS4PWE5/PSDDQM5/PBS5PWE6/PSDDQM6/PBS6PWE7/PSDDQM7/PBS7PSDA10/PGPL0PSDWE/PGPL1POE/PSDRAS/PGPL2PSDCAS/PGPL3PGTA/PUPMWAIT/PGPL4PSDAMUX/PGPL5PCI_MODE 1PCI_CFG0 (PCI_HOST_EN)MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

Ball

MPC8272/MPC8271 Only

AE22AE23AF12AD15AF16AF15AE15AE14AC17AD14AD13AE20AF14AD20AE13AF21AF22AE21AB14AC22AF7AE10AB10AD10AE9AF8AC10AE11AB11AF10AF9

PCI_CFG1 (PCI_ARB_EN)PCI_CFG2 (DLL_ENABLE)

PCI_ PARPCI_FRAMEPCI_TRDYPCI_IRDYPCI_STOPPCI_DEVSELPCI_IDSELPCI_PERRPCI_SERRPCI_REQ0PCI_REQ1/CPCI_HS_ESPCI_GNT0PCI_GNT1/CPCI_HS_LEDPCI_GNT2/CPCI_HS_ENUMPCI_RSTPCI_INTAPCI_REQ2DLLOUTPCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9PCI_AD10

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

PCI_AD11PCI_AD12PCI_AD13PCI_AD14PCI_AD15PCI_AD16PCI_AD17PCI_AD18PCI_AD19PCI_AD20PCI_AD21PCI_AD22PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27PCI_AD28PCI_AD29PCI_AD30PCI_AD31PCI_C0/BE0PCI_C1/BE1PCI_C2/BE2PCI_C3/BE3IRQ0/NMI_OUTTRST 2TCKTMSTDITDO

Ball

MPC8272/MPC8271 Only

AB12AC12AD12AF11AB13AE16AF17AD16AC16AF18AB16AD17AF19AB17AF20AE19AC18AB18AD19AD21AC20AE12AF13AC15AE18A17E21B22C23B24A22

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

TRISPORESET2/PCI_RSTHRESETSRESETRSTCONFMODCK1/RSRV/TC0/BNKSEL0MODCK2/CSE0/TC1/BNKSEL1MODCK3/CSE1/TC2/BNKSEL2

CLKIN1PA8/SMRXD2PA9/SMTXD2

PA10/MSNUM5PA11/MSNUM4PA12/MSNUM3PA13/MSNUM2

PA14/FCC1_MII_HDLC_RXD3PA15/FCC1_MII_HDLC_RXD2PA16/FCC1_MII_HDLC_RXD1PA17/FCC1_MII_HDLC_RXD0/

FCC1_MII_TRAN_RXD/FCC1_RMII_RX

D0PA18/FCC1_MII_HDLC_TXD0/FCC1_M

II_TRAN_TXD/FCC1_RMII_TXD0PA19/FCC1_MII_HDLC_TXD1/FCC1_R

MII_TXD1

PA20/FCC1_MII_HDLC_TXD2PA21/FCC1_MII_HDLC_TXD3

PA22PA23PA24/MSNUM1PA25/MSNUM0

PA26/FCC1_MII_RMIIRX_ER

FCC1_UT_RXD0FCC1_UT_RXD1FCC1_UT_RXD2FCC1_UT_RXD3FCC1_UT_RXD4FCC1_UT_RXD5FCC1_UT_RXD6FCC1_UT_RXD7

Ball

MPC8272/MPC8271 Only

B23C24D22F22A24A20C20A21D21AF25 3AA223AB233AD263AD253AA243W223Y243T223W263

FCC1_UT_TXD7

V263

FCC1_UT_TXD6FCC1_UT_TXD5FCC1_UT_TXD4FCC1_UT_TXD3FCC1_UT_TXD2FCC1_UT_TXD1FCC1_UT_TXD0FCC1_UT_RXCLAV

R233P253N223N263N233H263G253L223

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

Freescale Semiconductor

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

PA27/FCC1_MII_RX_DV/FCC1_RMII_C

RS_DV

PA28/FCC1_MII_RMII_TX_ENPA29/FCC1_MII_TX_ERPA30/FCC1_MII_CRS/FCC1_RTSPA31/FCC1_MII_COL

Ball

MPC8272/MPC8271 Only

FCC1_UT_RXSOCFCC1_UT_RXENBFCC1_UT_TXSOCFCC1_UT_TXCLAVFCC1_UT_TXENBG243G233B263A253G223T253P223L253J263U233U263M243M233H243E253D263K213D243E233AF233AD233AB223AE243AF243AE263AC243AA233AB253V223AA263

PB18/FCC2_MII_HDLC_RXD3PB19/FCC2_MII_HDLC_RXD2PB20/FCC2_MII_HDLC_RMII_RXD1

PB21/FCC2_MII_HDLC_RMII_RXD0/FCC2_TRAN_RXDPB22/FCC2_MII_HDLC_TXD0/FCC2_TRAN_TXD/

FCC2_RMII_TXD0PB23/FCC2_MII_HDLC_TXD1/FCC2_RMII_TXD1PB24/FCC2_MII_HDLC_TXD2/L1RSYNCB2PB25/FCC2_MII_HDLC_TXD3/L1TSYNCB2

PB26/FCC2_MII_CRS/L1RXDB2PB27/FCC2_MII_COL/L1TXDB2

PB28/FCC2_MII_RMII_RX_ER/FCC2_RTS/TXD1PB29/FCC2_MII_RMII_TX_EN

PB30/FCC2_MII_RX_DV/FCC2_RMII_CRS_DV

PB31/FCC2_MII_TX_ER

PC0/DREQ3/BRGO7/SMSYN1/L1CLKOA2PC1/BRGO6/L1RQA2PC4/SMRXD1/SI2_L1ST4/FCC2_CDPC5/SMTXD1/SI2_L1ST3/FCC2_CTSPC6/FCC1_CD/SI2_L1ST2PC7/FCC1_CTSFCC1_UT_RXADDR2FCC1_UT_TXADDR2

PC8/CD4/RTS1/SI2_L1ST2/CTS3PC9/CTS4/L1TSYNCA2PC10/CD3/USB_RNPC11/CTS3/USB_RP/L1TXD3A2PC12

FCC1_UT_RXADDR1

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

PC13/BRGO5PC14/CD1PC15/CTS1PC16/CLK16

PC17/CLK15/BRGO8/DONE2PC18/CLK14/TGATE2PC19/CLK13/BRGO7/TGATE1PC20/CLK12/USBOEPC21/CLK11/BRGO6/CP_INT

PC22/CLK10/DONE3FCC1_UT_TXPRTY

Ball

MPC8272/MPC8271 Only FCC1_UT_TXADDR1FCC1_UT_RXADDR0FCC1_UT_TXADDR0

V233W243U243T233T263R263P243L263L243L233K243K233F263H233K223D253F243AB213AC263Y233

FCC1_UT_TXPRTYFCC1_UT_RXPRTYFCC1_UT_RXADDR4FCC1_UT_TXADDR4

AA253Y263W253V253R243P233N253K263K253J253C263

PC23/CLK9/BRGO5/DACK3/CD1PC24/CLK8/TIN3/TOUT4/DREQ2/BRGO1PC25/CLK7/BRGO4/DACK2/SPISELPC26/CLK6/TOUT3/TMCLKPC27/CLK5/BRGO3/TOUT1FCC1_UT_RXPRTY

PC28/CLK4/TIN1/TOUT2/SPICLKPC29/CLK3/TIN2/BRGO2/CTS1PD7/SMSYN2

PD14/I2CSCLPD15/I2CSDA

PD16/SPIMISOPD17/BRGO2/SPIMOSI

PD18/SPICLKPD19/SPISEL/BRGO1

FCC1_UT_TXADDR3

PD20/RTS4/L1RSYNCA2PD21/TXD4/L1RXD0A2PD22/RXD4/L1TXD0A2PD23/RTS3/USB_TPPD24/TXD3/USB_TNPD25/RXD3/USB_RXD

PD29/RTS1FCC1_UT_RXADDR3

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Pinout

Table20. Pinout (continued)

Pin Name

MPC8272/MPC8248 and MPC8271/MPC8247

PD30/TXD1PD31/RXD1VCCSYNVCCSYN1CLKIN2No connect 4I/O power

Ball

MPC8272/MPC8271 Only

E243B253C18K6C21

D194, J34, AD24 5

B4, F3, J2, N4, AD1, AD5, AE8, AC13, AD18, AB24, AB26, W23, R25, M25, F25, C25, C22, B17, B12, B8, E6, F6, H6, L5, L6, P6, T6, U6, V5, Y5, AA6, AA8, AA10, AA11, AA14, AA16, AA17, AB19, AB20, W21, U21, T21, P21, N21, M22, J22, H21, F21, F19, F17, E16, F14, E13, E12, F10, E10, E9

F5, K5, M5, AA5, AB7, AA13, AA19, AA21, Y22, AC25, U22, R22, L21, H22, E22, E20, E15, F13, F11, F8, L3, V4, W3, AC11, AD11, AB15, U25, T24, J24, H25, F23, B19, D17, C17, D10, C10

E19, E2, K1, Y2, AE1, AE4, AD9, AC14, AE17, AC19, AE25, V24, P26, M26, G26, E26, B21, C12, C11, C8, A8, B18, A18, A2, B1, B2, A5, C5, D4, D6, G2, L4, P1, R1, R4, AC4, AE7, AC23, Y25, N24, J23, A23, D23, D20, E18, A13, A16, K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11,R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17

Core Power

Ground

1 Must be tied to ground.

2 Should be tied to VDDH via a 2K Ω external pull-up resistor.3

This pin is not connected. It should be left floating.5 Must be pulled down or left floating

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Package

9Package

Transfer molding compoundPlated substrate viaFigure13 shows the side profile of the PBGA package.

Die attachWire bondsBall bondScreen-printedsolder maskCu substrate tracesDIE1 mm pitchResin glass epoxyFigure13. Side View of the PBGA Package Remove

Table21 provides package parameters. Figure14 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA package.

Table21. Package Parameters

CodeVR, ZQ

TypePBGA

Outline (mm)27 x 27

Interconnects

516

Pitch (mm)1

Nominal Unmounted

Height (mm)

2.25

NOTE: Temperature Reflow for the VR Package

In the VR package, sphere composition is lead-free (refer to Table2). This requires higher temperature reflow than what is required for other PowerQUICCII packages. Users should consult “Freescale PowerQUICCII™ Pb-Free Packaging Information”

(MPC8250PBFREEPKG) available at www.freescale.com.

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Package

Figure14. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Ordering Information

10Ordering Information

Figure15 provides an example of the Freescale part numbering nomenclature for the MPC8272. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For more information, contact a local Freescale sales office.

Product CodeDevice NumberTemperature RangeBlank = 0 to 105 °CC = –40 to 105 °C

Package

ZQ = 516 PBGA (lead spheres)VR = 516 PBGA (no lead spheres)

MPC82XXCVRXXXX

Die Revision Level

CPU/CPM/Bus Frequency (MHz)

B = 66E = 100F = 133I = 200M = 266P = 300T = 400

Figure15. Freescale Part Number Key

11Document Revision History

Table22 lists significant changes between revisions of this hardware specification.

Table22. Document Revision History

Revision

Date

Substantive Changes

12/2008 •Modified Figure5, “SCC/SMC/SPI/I2C External Clock Diagram,” and added second section of

figure notes.

•InTable11, modified “Data bus in pipeline mode” row and showed 66 MHz as “N/A.”•InSection10, “Ordering Information,” added “F = 133” to CPU/CPM/Bus Frequency.

•Added footnote concerning CPM_CLK/PCI_CLK ratio to column “PCI Division Factor” in Table16, “Clock Configurations for PCI Host Mode (PCI_MODCK=0),” and Table17, “Clock Configurations for PCI Host Mode (PCI_MODCK=1),.”

•Removed overbar from DLL_ENABLE in Table20, “Pinout.”12/2006 •Section6, “AC Electrical Characteristics,” removed deratings statement and clarified AC

timing descriptions.05/2006 •Added row for 133 MHz configurations to Table7.02/2006 •Inserted Section6.3, “JTAG Timings.”

09/2005 •Added 133-MHz to the list of frequencies in the opening sentence of Section6, “AC Electrical

Characteristics”.

•Added 133 MHz columns to Table9, Table10, Table11, and Table12. •Added footnote 2 to Table12.

•Added the conditions note directly above Table11.

1.51.41.31.2

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Document Revision History

Table22. Document Revision History (continued)

Revision1.11.0

Date

Substantive Changes

01/2005 •Modification for correct display of assertion level (“overbar”) for some signals12/2004 •

• • • •

• • • • • • • • • • • • • • • • • •

Section 1.1: Added 8:1 ratio to Internal CPM/bus clock multiplier valuesSection 2: removed voltage tracking note

Table3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on resetTable4: Updated VDD and VCCSYN to 1.425 V - 1.575 V

Table5: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external pullup removed.

Section 4.6: Updated description of layout practices Table5: Note 3 added regarding IIC compatibility

Table7: Updated nominal and maximum power dissipation values

Table8: updated PCI impedance to 27Ω, updated 60x and MEMC values and added note to reflect configurable impedance

Section 6: Added sentence providing derating factor

Section 6.1: added Note: Rise/Fall Time on CPM Input Pins

Table9: updated values for following specs: sp36b, sp37a, sp38a, sp39a, sp38b, sp40, sp41, sp42, sp43, sp42a

Table10: updated values for following specs: sp16a, sp16b, sp18a, sp18b, sp20, sp21, sp22Section 6.2: added spread sprectrum clocking noteSection 6.2: added CLKIN jitter note

Table11: combined specs sp11 and sp11a

Table12: sp30 Data Bus minimum delay values changed to 0.8Section 7: unit of ns added to Tval notes

Section 7: Updated all notes to reflect updated CPU Fmin of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.

Section7, “Clock Configuration Modes”: Updated all table footnotes reflect updated CPU Fmin of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.Table20: correct superscript of footnote number after pin AD22Table20: remove DONE3 from PC12

Table20: signals referring to TDMs C2 and D2 removed

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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Document Revision History

Table22. Document Revision History (continued)

Revision0.2

Date12/2003 •

• • • •

Substantive Changes

Table1: NewTable2: New

Table4: Modification of VDD and VCCSYN to 1.45–1.60 V

Table5: Addition of note 2 regarding TRST and PORESET (see VIH row of Table5)Table5 and Table20: Addition of muxed signalsCPCI_HS_ES to PCI_REQ1 (AF14)CPCI_HS_LED to PCI_GNT1 (AE13)CPCI_HS_ENUM to PCI_GNT2 (AF21)Table5 and Table20: Modification of PCI signal names for consistency with PCI signal names on other PowerQUICC II devices: PCI_CFG0 (PCI_HOST_EN) (AC21)PCI_CFG1 (PCI_ARB_EN) (AE22)PCI_CFG2 (DLL_ENABLE) (AE23)PCI_PAR (AF12)PCI_FRAME (AD15)PCI_TRDY(AF16)PCI_IRDY (AF15)PCI_STOP (AE15)DEVSEL (AE14)PCI_IDSEL (AC17)PCI_PERR (AD14)PCI_SERR (AD13)PCI_REQ0–2 (AAE20, AF14, AB14)PCI_GNT0–2 (AD20, AE13, AF21)PCI_RST (AF22)PCI_INTA (AE21)PCI_C0-3 (AE12, AF13, AC15, AE18)PCI_AD0-31

Table5 and Table20: Corrected assertion level (added ““) PCI_HOST_EN (AC21) and PCI_ARB_EN (AE22)Table6: Addition of RθJT and note 4

Sections 4.1–4.5 and 4.7 on thermal characteristics: New

Section7, “Clock Configuration Modes”: Modification to first paragraph. Note that

PCI_MODCK is a bit in the Hard Reset Configuration Word. It is not an input signal as it is in the MPC8280 Family and MPC8260 Family.

Addition of “Note: Temperature Reflow for the VR Package\" on page 55Table20: Addition of note 2 to TRST (E21) and PORESET (C24)Table20: Removal of Thermal0 (D19) and Thermal1(J3). These pins are now “No connects.” Note4 unchanged.

Table20: Removal of Spare0 (AD24). This pin is now a “No connect.” Note 5 unchanged.Table20: Addition of PCI_MODE (AD22). This pin was previously listed as “Ground.” Addition of note 1.

•

• • • •

• • • • •

0.1

9/2003

• • • • •

Addition of the MPC8271 and the MPC8247 (these devices do not have a security engine) Table5: Addition of note 2 to VIH

Table5: Changed IOL for 60x signals to 6.0 mA

Modification of note 1 for Table16, Table17, Table18, and Table19

Table20: Addition of ball AD9 to GND. In rev 0 of this document, AD8 was listed as assigned to both CS5 and GND. AD8 is only assigned to CS5. •Table20: Addition of note 4 to Thermal0 (D19) and Thermal1(J3) •Addition of ZQ package code to Figure15

05/2003 NDA release

MPC8272 PowerQUICC II™ Family Hardware Specifications,Rev. 2

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