AD9235_datasheet(1)

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Data Sheet

FEATURES

Single 3 V supply operation (2.7 V to 3.6 V) SNR = 70 dBc to Nyquist at 65 MSPS SFDR = 85 dBc to Nyquist at 65 MSPS Low power: 300 mW at 65 MSPS

Differential input with 500 MHz bandwidth On-chip reference and SHA DNL = ±0.4 LSB

Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer

APPLICATIONS

Ultrasound equipment

IF sampling in communications receivers IS-95, CDMA-One, IMT-2000 Battery-powered instruments Hand-held scopemeters

Low cost digital oscilloscopes

GENERAL DESCRIPTION

The AD9235 is a family of monolithic, single 3 V supply, 12-bit, 20/40/65 MSPS analog-to-digital converters (ADCs). This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9235 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20/40/65 MSPS data rates and guarantee no missing codes over the full operating temperature range.

The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9235 is suitable for applications in communica-tions, imaging, and medical ultrasound.

A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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12-Bit, 20/40/65 MSPS 3 V A/D Converter

AD9235 FUNCTIONAL BLOCK DIAGRAM

AVDDDRVDDVIN+8-STAGESHAMDAC11 1/2-BITA/DVIN–PIPELINEREFT4163A/DREFBCORRECTION LOGIC12OUTPUT BUFFERSOTRAD9235D11VREFD0CLOCKSENSEDUTY CYCLEMODESTABILIZERSELECTREFSELECT0.5V100-1AGNDCLKPDWNMODEDGND20

Figure 1.

can be used with the most significant bit to determine low or high overflow.

Fabricated on an advanced CMOS process, the AD9235 is avail-able in a 28-lead TSSOP and a 32-lead LFCSP and is specified over the industrial temperature range (–40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9235 operates from a single 3 V power supply and features a separate digital output driver supply to accommo-date 2.5 V and 3.3 V logic families.

2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW. 3. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and can be configured for single-ended or differential operation.

4. The AD9235 pinout is similar to the AD9214-65, a 10-bit, 65 MSPS ADC. This allows a simplified upgrade path from 10 bits to 12 bits for 65 MSPS systems.

5. The clock DCS maintains overall ADC performance over a wide range of clock pulse widths.

6. The OTR output bit indicates when the signal is beyond the selected input range.

AD9235

Data Sheet

Applying the AD9235 .................................................................... 15 Theory of Operation .................................................................. 15 Analog Input ............................................................................... 15 Clock Input Considerations ...................................................... 16 Power Dissipation and Standby Mode .................................... 17 Digital Outputs ........................................................................... 18 Voltage Reference ....................................................................... 18 Operational Mode Selection ..................................................... 19 TSSOP Evaluation Board .......................................................... 19 LFCSP Evaluation Board ........................................................... 20 Outline Dimensions ....................................................................... 36 Ordering Guide .......................................................................... 37

TABLE OF CONTENTS Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 4 Switching Specifications .............................................................. 4 AC Specifications .......................................................................... 5 Absolute Maximum Ratings ............................................................ 7 Explanation of Test Levels ........................................................... 7 ESD Caution .................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Definitions of Specifications ........................................................... 9 Equivalent Circuits ......................................................................... 10 Typical Performance Characteristics ........................................... 11

REVISION HISTORY

10/12—Rev. C to Rev. D

Changes to Figure 4 and Table 6 ................................................................ 8 Updated Outline Dimensions (Changed CP-32-2 to CP-32-7) ..... 36 Changes to Ordering Guide .......................................................... 37 10/04—Data Sheet changed from Rev. B to Rev. C

Changes to Format ............................................................. Universal Changes to Specifications ................................................................. 3 Changes to the Ordering Guide .................................................... 37 5/03—Data Sheet changed from Rev. A to Rev. B

Added CP-32 Package (LFCSP) ........................................ Universal Changes to Several Pin Names.......................................... Universal Changes to Features ........................................................................... 1 Changes to Product Description ..................................................... 1 Changes to Product Highlights ........................................................ 1 Changes to Specifications ................................................................. 2 Replaced Figure 1 .............................................................................. 3 Changes to Absolute Maximum Ratings ........................................ 5 Changes to Ordering Guide ............................................................. 5 Changes to Pin Function Descriptions ........................................... 6 New Definitions of Specifications Section ..................................... 7

Changes to TPCs 1 to 12 .................................................................. 9

Changes to Theory of Operation Section..................................... 13 Changes to Analog Input Section .................................................. 13 Changes to Single-ended Input Configuration Section ............. 14 Replaced Figure 8 ............................................................................ 14 Changes to Clock Input Considerations Section ........................ 14 Changes to Table I ........................................................................... 15 Changes to Power Dissipation and Standby Mode Section ....... 15 Changes to Digital Outputs Section .............................................. 15 Changes to Timing Section ............................................................ 15 Changes to Figure 13 ....................................................................... 16 Changes to Figures 16 to 26 ........................................................... 17 Added LFCSP Evaluation Board Section ..................................... 17 Inserted Figures 27 to 35 ................................................................ 25 Added Table III ................................................................................ 30 Updated Outline Dimensions ........................................................ 31 8/02—Data Sheet changed from Rev. 0 to Rev. A

Updated RU-28 Package ................................................................ 24

Rev. D | Page 2 of 40

Data Sheet

AD9235

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 1.

Parameter RESOLUTION ACCURACY

No Missing Codes Guaranteed Offset Error Gain Error1

Differential Nonlinearity (DNL)2

Integral Nonlinearity (INL)2

TEMPERATURE DRIFT Offset Error Gain Error

INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA

Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT

Input Span, VREF = 0.5 V Input Span, VREF = 1.0 V Input Capacitance3

REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD

Supply Current IAVDD2 IDRVDD2 PSRR

POWER CONSUMPTION DC Input4

Sine Wave Input2 Standby Power5

Temp Full Full Full Full Full 25°C Full 25°C Full Full Full Full Full Full 25°C 25°C Full Full Full Full Full Full Full Full Full Full Full Full

Test Level VI VI VI VI IV I IV I V V VI V V V V V IV IV V V IV IV V V V V VI V

AD9235BRU/BCP-20 Min Typ Max 12 12 ±0.30 ±1.20 ±0.30 ±2.40 ±0.35 ±0.65 ±0.35 ±0.45 ±0.80 ±0.40 ±2 ±12 ±5 ±35 0.8 ±2.5 0.1 0.54 0.27 1 2 7 7 2.7 3.0 3.6 2.25 3.0 3.6 30 2 ±0.01 90 95 110 1.0 AD9235BRU/BCP-40

Min Typ Max 12 12 ±0.50 ±1.20 ±0.50 ±2.50 ±0.35 ±0.75 ±0.35 ±0.50 ±0.90 ±0.40 ±2 ±12 ±5 ±35 0.8 ±2.5 0.1 0.54 0.27 1 2 7 7 2.7 3.0 3.6 2.25 3.0 3.6 55 5 ±0.01 165 180 205 1.0 AD9235BRU/BCP-65

Min Typ Max 12 12 ±0.50 ±1.20 ±0.50 ±2.60 ±0.40 ±0.80 ±0.35 ±0.70 ±1.30 ±0.45 ±3 ±12 ±5 ±35 0.8 ±2.5 0.1 0.54 0.27 1 2 7 7 2.7 3.0 3.6 2.25 3.0 3.6 100 7 ±0.01 300 320 350 1.0

Unit

Bits Bits % FSR % FSR LSB LSB LSB LSB

ppm/°C ppm/°C mV mV mV mV

LSB rms LSB rms

V p-p V p-p pF kΩ V V mA mA % FSR mW mW mW

Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4

Measured with dc input at maximum clock rate. 5

Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).

Rev. D | Page 3 of 40

AD9235

Data Sheet

DIGITAL SPECIFICATIONS

Table 2.

Parameter LOGIC INPUTS

High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS1 DRVDD = 3.3 V

High-Level Output Voltage (IOH = 50 µA)

High-Level Output Voltage (IOH = 0.5 mA)

Low-Level Output Voltage (IOL = 1.6 mA)

Low-Level Output Voltage (IOL = 50 µA) DRVDD = 2.5 V

High-Level Output Voltage (IOH = 50 µA)

High-Level Output Voltage (IOH = 0.5 mA)

Low-Level Output Voltage (IOL = 1.6 mA)

Low-Level Output Voltage (IOL = 50 µA)

Temp Full Full Full Full Full Full Full Full Full Full Full Full Full

Test Level IV IV IV IV V IV IV IV IV IV IV IV IV

AD9235BRU/BCP-20 Min Typ Max 2.0 0.8 –10 +10 –10 +10 2 3.29 3.25 0.2 0.05 2.49 2.45 0.2 0.05 AD9235BRU/BCP-40

Min Typ Max 2.0 0.8 –10 +10 –10 +10 2 3.29 3.25 0.2 0.05 2.49 2.45 0.2 0.05 AD9235BRU/BCP-65

Min Typ Max 2.0 0.8 –10 +10 –10 +10 2 3.29 3.25 0.2 0.05 2.49 2.45 0.2 0.05

Unit

V V µA µA pF V V V V V V V V

Output voltage levels measured with 5 pF load on each output.

SWITCHING SPECIFICATIONS

Table 3.

Parameter

CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period

CLK Pulse-Width High1 CLK Pulse-Width Low1 DATA OUTPUT PARAMETERS Output Delay2 (tPD)

Pipeline Delay (Latency) Aperture Delay (tA)

Aperture Uncertainty Jitter (tJ) Wake-Up Time3

OUT-OF-RANGE RECOVERY TIME

Temp Full Full Full Full Full Full Full Full Full Full Full

Test Level VI V V V V V V V V V V

AD9235BRU/BCP-20 Min Typ Max 20 1 50.0 15.0 15.0 3.5 7 1.0 0.5 3.0 1 AD9235BRU/BCP-40

Min Typ Max 40 1 25.0 8.8 8.8 3.5 7 1.0 0.5 3.0 1 AD9235BRU/BCP-65

Min Typ Max 65 1 15.4 6.2 6.2 3.5 7 1.0 0.5 3.0 2

Unit

MSPS MSPS ns ns ns ns Cycles ns ps rms ms Cycles

For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models. Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3

Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.

Rev. D | Page 4 of 40

Data Sheet

NN–1ANALOGINPUTN+1N+2N+3N+4N+7N+5N+6N+8AD9235

tACLKDATAOUTN–9N–8N–7N–6N–5N–4N–3N–2N–1NtPD = 6.0ns MAX2.0ns MIN02461-002

Figure 2. Timing Diagram

AC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = –0.5 dBFS, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 4.

Parameter

SIGNAL-TO-NOISE RATIO fINPUT = 2.4 MHz fINPUT = 9.7 MHz

fINPUT = 19.6 MHz

fINPUT = 32.5 MHz

fINPUT = 100 MHz

SIGNAL-TO-NOISE RATIO AND DISTORTION fINPUT = 2.4 MHz fINPUT = 9.7 MHz

fINPUT = 19.6 MHz

fINPUT = 32.5 MHz

fINPUT = 100 MHz

TOTAL HARMONIC DISTORTION fINPUT = 2.4 MHz fINPUT = 9.7 MHz

fINPUT = 19.6 MHz

fINPUT = 32.5 MHz

fINPUT = 100 MHz WORST HARMONIC (SECOND OR THIRD) fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz

Temp 25°C Full 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C Full 25°C 25°C Full Full Full

Test Level V IV I IV I IV I V V IV I IV I IV I V V IV I IV I IV I V IV IV IV

AD9235BRU/BCP-20 Min Typ Max 70.8 70.0 70.4 70.6 68.7 69.9

70.6 70.3 70.5 68.6

–88.0 –86.0 –87.4

–84.0 –90.0

–79.0 –80.0

AD9235BRU/BCP-40 Min Typ Max 70.6 69.9 70.3 70.4 68.5 69.7

70.5 70.2 70.3 68.3

–.0

–85.5 –86.0

–82.5

–90.0

–79.0

–80.0

AD9235BRU/BCP-65 Min Typ Max 70.5 68.7 69.7 70.1 68.3 68.3

70.4 69.5 69.9 67.8

–87.5

–81.8 –82.0 –78.0

–83.5

–74.0

Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc

Rev. D | Page 5 of 40

AD9235

Data Sheet

Temp 25°C Full 25°C Full 25°C Full 25°C 25°C

Test Level V IV I IV I IV I V

AD9235BRU/BCP-20 Min Typ Max 92.0 80.0 88.5 91.0 84.0

AD9235BRU/BCP-40

Min Typ Max 92.0 80.0 .0 90.0 85.0

AD9235BRU/BCP-65

Min Typ Max 92.0 74.0 83.0 85.0 80.5

Unit dBc dBc dBc dBc dBc dBc dBc dBc

Parameter

SPURIOUS-FREE DYNAMIC RANGE fINPUT = 2.4 MHz fINPUT = 9.7 MHz

fINPUT = 19.6 MHz

fINPUT = 32.5 MHz

fINPUT = 100 MHz

Rev. D | Page 6 of 40

Data Sheet

AD9235

ABSOLUTE MAXIMUM RATINGS

Table 5.

Pin Name ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs CLK, MODE AGND VIN+, VIN– AGND VREF AGND SENSE AGND REFB, REFT AGND PDWN AGND

ENVIRONMENTAL

Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature

With

Respect to

AGND DGND DGND DRVDD DGND

Min –0.3 –0.3 –0.3 –3.9 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –40 –65

Max +3.9 +3.9 +0.3 +3.9

DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +85 150 300 +150

Unit V V V V V V V V V V V °C °C °C °C

Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

EXPLANATION OF TEST LEVELS

Test Levels I II III IV V VI

Description

100% production tested.

100% production tested at 25°C and sample tested at specified temperatures. Sample tested only.

Parameter is guaranteed by design and characteriza-tion testing.

Parameter is a typical value only.

100% production tested at 25°C; guaranteed by de-sign and characterization testing for industrial tem-perature range; 100% production tested at tempera-ture extremes for military devices.

Typical thermal impedances (28-lead TSSOP), θJA = 67.7°C/W; (32-lead

LFCSP), θJA = 32.5°C/W, θJC = 32.71°C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-1.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. D | Page 7 of 40

AD9235

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OTR1MODE2SENSE3VREF4REFB5REFT6AVDD7AGND8VIN+928D11 (MSB)27D1026D925D8AD9235TOP VIEW(Not to Scale)24DRVDD23DGND22D721D620D519D418DNCCLKDNCPDWNDNCDNCD0 (LSB)D11234567832AVDD31AGND30VIN–29VIN+28AGND27AVDD26REFT25REFB2423222120191817AD9235TOP VIEW(Not to Scale)VREFSENSEMODEOTRD11 (MSB)D10D9D8VIN–10AGND11AVDD12CLK13PDWN1417D202461-0031615D1D0 (LSB)

NOTES1.DNC = DO NOT CONNECT.2.IT IS RECOMMENDED THAT THE EXPOSED PADDLEBE SOLDERED TO THE GROUND PLANE.D2D3D4D5D6D7DGNDDRVDDD391011121314151602461-004

Figure 3. 28-Lead TSSOP Pin Configuration

Figure 4. 32-Lead LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

28-Lead TSSOP 1 2 3 4 5 6 7, 12 8, 11 9 10 13 14

15 to 22, 25 to 28 23 24

Pin No.

32-Lead LFCSP 21 22 23 24 25 26 27, 32 28, 31 29 30 2 4

7 to 14, 17 to 20 15 16

1, 3, 5, 6 EP

Mnemonic OTR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN– CLK PDWN

D0 (LSB) to D11 (MSB) DGND DRVDD DNC EPAD

Description

Out-of-Range Indicator.

Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection. Reference Mode Selection.

Voltage Reference Input/Output. Differential Reference (−). Differential Reference (+). Analog Power Supply. Analog Ground. Analog Input Pin (+). Analog Input Pin (−). Clock Input Pin.

Power-Down Function Selection (Active High). Data Output Bits.

Digital Output Ground.

Digital Output Driver Supply. Must be decoupled to DGND with a minimum. 0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF. Do Not Connect.

Exposed Pad. It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maxi-mum thermal capability of the package is achieved with exposed paddle soldered to the customer board.

Rev. D | Page 8 of 40

Data Sheet

AD9235

Signal-to-Noise and Distortion (SINAD)1

The ratio of the rms signal amplitude (set 0.5 dB below full scale) to the rms value of the sum of all other spectral compo-nents below the Nyquist frequency, including harmonics but excluding dc.

Effective Number of Bits (ENOB)

The ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD using the following formula

N = (SINAD − 1.76)/6.02

Signal-to-Noise Ratio (SNR)1

The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral compo-nents below the Nyquist frequency, excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)1

The difference in dB between the rms amplitude of the input signal and the peak spurious signal.

Two-Tone SFDR1

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.

Clock Pulse Width and Duty Cycle

Pulse-width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse-width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The clock rate at which parametric testing is performed. Output Propagation Delay (tPD)

The delay between the clock logic threshold and the time when all bits are within valid logic levels.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

DEFINITIONS OF SPECIFICATIONS

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay (tA)

The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Jitter (tJ)

The sample-to-sample variation in aperture delay.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1 ½ LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges.

Offset Error

The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN–. Offset error is defined as the deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1 ½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

Temperature Drift

The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX.

Power Supply Rejection Ratio

The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

Total Harmonic Distortion (THD)1

The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. 1

AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).

Rev. D | Page 9 of 40

AD9235

EQUIVALENT CIRCUITS

AVDDVIN+, VIN–500-120

Figure 5. Equivalent Analog Input Circuit

AVDDMODE20kΩ600-120

Figure 6. Equivalent MODE Input Circuit

Rev. D | Page 10 of 40

Data Sheet

DRVDDD11–D0,OTR700-120

Figure 7. Equivalent Digital Output Circuit

AVDDCLK,PDWN800-120

Figure 8. Equivalent Digital Input Circuit

Data Sheet

AD9235

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.0 V, DRVDD = 2.5 V, fSAMPLE = 65 MSPS with DCS disabled, TA = 25°C, 2 V differential input, AIN = −0.5 dBFS, VREF = 1.0 V, unless otherwise noted.

0SNR = 70.3dBcSINAD = 70.2dBcENOB = 11.4 BITSTHD =–86.3dBcSFDR = .9dBc100959085SFDR (2V DIFF)–20MAGNITUDE (dBFS)–40SNR/SFDR (dBc)807570656055SFDR (2V SE)SNR (2V DIFF)SNR (2V SE)–60–80–10002461-00906.513.019.5FREQUENCY (MHz)26.032.545

5055SAMPLE RATE (MSPS)606502461-01202461-01302461-014–1205040

Figure 9. Single Tone 8K FFT with fIN = 10 MHz

0100959085Figure 12. AD9235-65: Single Tone SNR/SFDR vs.

fCLK with fIN = Nyquist (32.5 MHz)

–20SNR = 69.4dBcSINAD = 69.1dBcENOB = 11.2 BITSTHD =–81.0dBcSFDR = 83.8dBcMAGNITUDE (dBFS)–40SNR/SFDR (dBc)SFDR (2V DIFF)SNR (2V SE)SNR (2V DIFF)80757065SFDR (2V SE)–60–80–100605571.578.084.5FREQUENCY (MHz)91.002461-010–12065.0502025

30SAMPLE RATE (MSPS)3540

Figure 10. Single Tone 8K FFT with fIN = 70 MHz

0SNR = 68.5dBcSINAD = 66.5dBcENOB = 10.8 BITSTHD =–71.0dBcSFDR = 71.2dBcFigure 13. AD9235-40: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (20 MHz)

100959085SFDR (2V SE)SFDR (2V DIFF)–20MAGNITUDE (dBFS)–40SNR/SFDR (dBc)807570656055SNR (2V DIFF)SNR (2V SE)–60–80–10002461-011–12097.5104.0110.5117.0FREQUENCY (MHz)123.5130.05005

10SAMPLE RATE (MSPS)1520

Figure 11. Single Tone 8K FFT with fIN = 100 MHz Figure 14. AD9235-20: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (10 MHz)

Rev. D | Page 11 of 40

AD9235

100SFDRSFDRSINGLE-ENDED (dBFS)DIFFERENTIAL (dBFS)90SFDR)cDIFFERENTIAL (dBc)BdSNR 80dDIFFERENTIAL (dBFS))ncaB Sd(F B70Rd(SNRDF RDSINGLE-ENDED (dBFS)S/RFS60SFDRNS/RNSINGLE-ENDED (dBc)SSNR50SINGLE-ENDED (dBc)SNRDIFFERENTIAL (dBc)4051–30–25–20–15–10–500-16A4IN (dBFS)20

Figure 15. AD9235-65: Single Tone SNR/SFDR vs.

AIN with fIN = Nyquist (32.5 MHz)

100SFDRDIFFERENTIAL (dBFS)90)SFDRSFDRcB80SNRDIFFERENTIALSINGLE-ENDEDd(dBFS) dDIFFERENTIAL(dBc))cna(dBFS)B dS( FB70RDdF(SNR SR/DSINGLE-ENDEDRF60(dBFS)NSSFDRS/RSNRNSINGLE-ENDED (dBc)SDIFFERENTIAL (dBc)50SNRSINGLE-ENDED (dBc)4061–30–25–20–15–10–500-16A4IN (dBFS)20

Figure 16. AD9235-40: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (20 MHz)

100SFDR DIFFERENTIAL (dBFS)90SFDRSFDRDIFFERENTIAL (dBc))cSINGLE-ENDED (dBFS)BdSFDR 80dSNRSINGLE-ENDED(dBc))nDIFFERENTIAL (dBFS)caB dS( FB70Rd(SNRDF RDSINGLE-ENDED (dBFS)S/RFS60N/RSNRSNDIFFERENTIAL(dBc)S50SNR40SINGLE-ENDED (dBc)71–30–25–20–15–10–500-16A4IN (dBFS)20

Figure 17. AD9235-20: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (10 MHz)

Rev. D | Page 12 of 40

Data Sheet

9590SFDR858075SNR70658102550751001250-16INPUT FREQUENCY (MHz)420

Figure 18. AD9235-65: SNR/SFDR vs. fIN

9590SFDR858075SNR70659102550751001250-16INPUT FREQUENCY (MHz)420

Figure 19. AD9235-40: SNR/SFDR vs. fIN

9590SFDR858075SNR70650202550751001250-16INPUT FREQUENCY (MHz)420

Figure 20. AD9235-20: SNR/SFDR vs. fIN

Data Sheet

0SNR = .6dBFSSFDR = 81.6dBFSAD9235

9590852V SFDR1V SFDR–20MAGNITUDE (dBFS)SNR/SFDR (dBFS)–408075706560–242V SNR1V SNR–60–80–10002461-02139.045.552.0FREQUENCY (MHz)58.565.0–21–18

–15AIN (dBFS)–12–9–602461-02402461-02502461-026–12032.5Figure 21. Dual Tone 8K FFT with fIN1 = 45 MHz and fIN2 = 46 MHz

0SNR = .3dBFSSFDR = 81.1dBFS

Figure 24. Dual Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz

9590852V SFDR1V SFDR–20MAGNITUDE (dBFS)SNR/SFDR (dBFS)–408075706560–242V SNR1V SNR–60–80–10002461-022–12065.071.578.084.5FREQUENCY (MHz)91.097.5–21–18

–15AIN (dBFS)–12–9–6Figure 22. Dual Tone 8K FFT with fIN1 = 69 MHz and fIN2 = 70 MHz

Figure 25. Dual Tone SNR/SFDR vs. AIN with fIN1 = 69 MHz and fIN2 = 70 MHz

9590852V SFDR1V SFDRSNR = 62.5dBFSSFDR = 75.6dBFS–20MAGNITUDE (dBFS)SNR/SFDR (dBFS)–408075706560–242V SNR1V SNR–60–80–100136.5143.0149.5FREQUENCY (MHz)156.0162.002461-023–120130.0–21–18

–15AIN (dBFS)–12–9–6

Figure 23. Dual Tone 8K FFT with fIN1 = 144 MHz and fIN2 = 145 MHz

Figure 26. Dual Tone SNR/SFDR vs. AIN with fIN1 = 144 MHz and fIN2 = 145 MHz

Rev. D | Page 13 of 40

AD9235

7512.2Data Sheet

201572AD9235-20:2V SINADAD9235-40:2V SINADAD9235-65:11.72V SINAD10GAIN DRAFT (ppm/°C)02461-027SINAD (dBc)AD9235-20:1V SINADAD9235-40:1V SINADENOB (Bits)6911.250–5–10–1502461-03002461-03102461-03266AD9235-65:1V SINAD10.76310.2609.7010402030SAMPLE RATE (MSPS)5060–20–40–200

2040TEMPERATURE (°C)6080Figure 27. SINAD vs. fCLK with fIN = Nyquist

90SFDR: DCS ON80SFDR: DCS OFFSINAD: DCS ON

Figure 30. A/D Gain vs. Temperature Using an External Reference

1.00.80.60.40.2SINAD/SFDR (dBc)7060SINAD: DCS OFFINL (LSB)606502461-0280–0.2–0.4–0.6–0.85040303540455055DUTY CYCLE (%)–1.0050010001500

20002500CODE300035004000Figure 28. SINAD/SFDR vs. Clock Duty Cycle

908580SFDR 2V DIFF

Figure 31. Typical INL

1.00.80.6SINAD/SFDR (dBc)7570656055SFDR 1V DIFF0.4SINAD 2V DIFFDNL (LSB)02461-0290.20–0.2–0.4–0.6–0.8SINAD 1V DIFF50–40–30–20–1001020304050SAMPLE RATE (MSPS)607080–1.005001000

150020002500CODE300035004000

Figure 29. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz

Figure 32. Typical DNL

Rev. D | Page 14 of 40

Data Sheet

AD9235

For best dynamic performance, the source impedances driving VIN+ and VIN– should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.

HAPPLYING THE AD9235

THEORY OF OPERATION

The AD9235 architecture consists of a front end SHA followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage

followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction log-ic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state.

T5pFVIN+CPARTT5pFVIN–CPART02461-033H

Figure 33. Switched-Capacitor SHA Input

An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as:

REFT = ½(AVDD + VREF) REFB = ½(AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage.

90THD 2.5MHz 2V DIFFANALOG INPUT

The analog input to the AD9235 is a differential switched capacitor SHA that has been designed for optimum perfor-mance while processing a differential input signal. The SHA input can support a wide common-mode range and maintain excellent performance, as shown in Figure 34. An input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance. Referring to Figure 33, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt

capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth.

–90–85–80THD 35MHz 2V DIFFSNR 2.5MHz 2V DIFF858075–75–70SNR (dBc)7065605550SNR 35MHz 2V DIFF–65–60–5500.51.01.52.0COMMON-MODE LEVEL (V)2.502461-034–503.0THD (dBc)

Figure 34. AD9235-65: SNR, THD vs. Common-Mode Level

Rev. D | Page 15 of 40

AD9235

Data Sheet

differential transformer coupling is the recommended input configuration, as shown in Figure 36.

AVDDVIN+The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. Maxi-mum SNR performance is achieved with the AD9235 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference volt-age. The minimum and maximum common-mode input levels are defined as:

VCMMIN = VREF/2

VCMMAX = (AVDD + VREF)/2

The minimum common-mode input level allows the AD9235 to accommodate ground-referenced inputs.

Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN–. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+ while a 1 V reference is applied to VIN–. The AD9235 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies and in the lower speed grade models (AD9235-40 and AD9235-20).

22Ω15pF2Vp-p49.9Ω22Ω1kΩ15pF0.1µF1kΩAD9235VIN–AGND02461-036

Figure 36. Differential Transformer-Coupled Configuration

The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion.

Single-Ended Input Configuration

A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is degra-dation in SFDR and in distortion performance due to the large input common-mode swing. However, if the source

impedances on each input are matched, there should be little effect on SNR performance. Figure 37 details a typical single-ended input configuration.

1kΩ1kΩ1kΩ10µF0.1µF1kΩ0.33µF2Vp-p49.9Ω22Ω15pF22Ω15pFAVDDVIN+Differential Input Configurations

As previously detailed, optimum performance is achieved while driving the AD9235 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

1Vp-p49.9Ω499Ω15pFAD81380.1µF1kΩ523Ω499Ω22Ω15pFAD9235VIN–AGND02461-037

Figure 37. Single-Ended Input Configuration

CLOCK INPUT CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result, may be sensi-tive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance char-acteristics. The AD9235 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the perfor-mance of the AD9235. As shown in Figure 30, noise and distor-tion performance are nearly flat over a 30% range of duty cycle. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate.

499Ω22ΩAVDDVIN+1kΩAD9235VIN–AGND02461-035

Figure 35. Differential Input Configuration Using the AD8138

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9235. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications,

Rev. D | Page 16 of 40

Data Sheet

AD9235

325300275250AD9235-65High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated by

TOTAL POWER (mW)SNR Degradation = −20 × log10[2π × fINPUT × tJ]

In the equation, the rms aperture jitter, tJ, represents the root-sum square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9235. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.

22520017515012510075500AD9235-2010203040SAMPLE RATE (MSPS)506002461-038AD9235-40

Figure 38. Total Power vs. Sample Rate with fIN = 10 MHz

For the AD9235-20 speed grade, the digital power consumption can represent as much as 10% of the total dissipation. Digital power consumption can be minimized by reducing the capaci-tive load presented to the output drivers. The data in Figure 38 was taken with a 5 pF load on each output driver.

The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency.

By asserting the PDWN pin high, the AD9235 is placed in standby mode. In this state, the ADC typically dissipates 1 mW if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9235 into its normal operational mode.

Low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 µF and 10 µF decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 38, the power dissipated by the AD9235 is proportional to its sample rate. The digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current can be calculated as

IDRVDD = VDRVDD × CLOAD × fCLK × N

where N is the number of output bits, 12 in the case of the AD9235. This maximum current occurs when every output bit switches on every clock cycle, i.e., a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the encode rate and the characteristics of the analog input signal.

Rev. D | Page 17 of 40

AD9235

Data Sheet

SENSE Voltage AVDD VREF

0.2 V to VREF AGND to 0.2 V

Internal Switch Position N/A SENSE SENSE

Internal Divider

Resulting VREF (V) N/A 0.5

0.5 × (1 + R2/R1) 1.0

Resulting Differential Span (V p-p) 2 × External Reference 1.0

2 × VREF (See Figure 40) 2.0

Table 7. Reference Configuration Summary

Selected Mode External Reference

Internal Fixed Reference Programmable Reference Internal Fixed Reference

DIGITAL OUTPUTS

The AD9235 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs may require external buffers or latches. As detailed in Table 8, the data format can be selected for either offset binary or twos complement.

SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as

VREF = 0.5 × (1 + R2/R1)

VIN+VIN–REFT0.1µFADCCORE0.1µFREFB0.1µFVREF10µF+0.1µFSELECTLOGICSENSE0.5V+10µFTiming

The AD9235 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propaga-tion delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram.

The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9235; these transients can detract from the converter’s dynamic performance.

The lowest typical conversion rate of the AD9235 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade.

AD923502461-039

Figure 39. Internal Reference Configuration

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the AD9235. The input range can be adjusted by varying the refer-ence voltage applied to the AD9235, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage).

In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.

VIN+VIN–REFT0.1µFADCCORE0.1µFREFB0.1µFVREF10µF+0.1µFR2SENSER1SELECTLOGIC0.5V+10µFInternal Reference Connection

A comparator within the AD9235 detects the potential at the SENSE pin and configures the reference into one of four possi-ble states, which are summarized in Table 7. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 39), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 40, the switch is again set to the

Rev. D | Page 18 of 40

AD923502461-040

Figure 40. Programmable Reference Configuration

Data Sheet

AD9235

OPERATIONAL MODE SELECTION

As discussed earlier, the AD9235 can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock DCS. The MODE pin is a multi-level input that controls the data format and DCS state. The input threshold values and corresponding mode selections are outlined in Table 8. Table 8. Mode Selection

MODE Voltage AVDD 2/3 AVDD 1/3 AVDD

AGND (Default)

Data Format

Twos Complement Twos Complement Offset Binary Offset Binary

Duty Cycle Stabilizer Disabled Enabled Enabled Disabled

External Reference Operation

The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift

characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 41 shows the typical drift characteris-tics of the internal reference in both 1 V and 0.5 V modes.

1.21.0VREF = 1.0VVREF ERROR (%)0.8VREF = 0.5V0.6The MODE pin is internally pulled down to AGND by a 20 kΩ resistor.

0.4TSSOP EVALUATION BOARD

The AD9235 evaluation board provides the support circuitry required to operate the ADC in its various modes and configu-rations. The converter can be driven differentially, through an AD8138 driver or a transformer, or single-ended. Separate pow-er pins are provided to isolate the DUT from the support cir-cuitry. Each input configuration can be selected by proper con-nection of various jumpers (refer to the schematics). Figure 43 shows the typical bench characterization setup used to evaluate the ac performance of the AD9235. It is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filter-ing of the input signal, to remove harmonics and lower the inte-grated noise at the input, is also necessary to achieve the speci-fied noise performance.

The AUXCLK input should be selected in applications requiring the lowest jitter and SNR performance, i.e., IF undersampling characterization. It allows the user to apply a clock input signal that is 4× the target sample rate of the AD9235. A low-jitter, differential divide-by-4 counter, the MC100LVEL33D, provides a 1× clock output that is subsequently returned back to the CLK input via JP9. For example, a 260 MHz signal (sinusoid) is divided down to a 65 MHz signal for clocking the ADC. Note that R1 must be removed with the AUXCLK interface. Lower jitter is often achieved with this interface since many RF signal generators display improved phase noise at higher output frequencies and the slew rate of the sinusoidal output signal is 4× that of a 1× signal of equal amplitude.

Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level.

2.02.53.002461-0420.201020304050TEMPERATURE (°C)60708002461-0410–40–30–20–10

Figure 41. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V.

If the internal reference of the AD9235 is used to drive multiple converters to improve gain matching, the loading of the refer-ence by the other converters must be considered. Figure 42 depicts how the internal reference voltage is affected by loading.

0.050–0.050.5V ERROR (%)ERROR (%)–0.101V ERROR (%)–0.15–0.20–0.25

00.51.01.5LOAD (mA)

Figure 42. VREF Accuracy vs. Load

Rev. D | Page 19 of 40

AD9235

Data Sheet

An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated in produc-tion. Designers interested in evaluating the op amp with the ADC should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 outputs and the AD9235 allows the user to optimize the frequency response of the op amp for the application.

LFCSP EVALUATION BOARD

The typical bench setup used to evaluate the ac performance of the AD9235 is similar to the TSSOP Evaluation Board connections (refer to the schematics for connection details). The AD9235 can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics).

3V–+–3V+–3V+–3V+REFINHP84, 2V p-pSIGNAL SYNTHESIZERBAND-PASSFILTERAVDDGNDDUTGNDDUTS4AVDDDRVDDXFMRINPUTDVDDDATACAPTUREANDPROCESSINGAD9235J102461-04310MHzREFOUTHP84, 2V p-pCLOCK SYNTHESIZERCLOCKDIVIDERS1CLOCKTSSOP EVALUATION BOARD

Figure 43. TSSOP Evaluation Board Connections

Rev. D | Page 20 of 40

Data Sheet

RP3 22ΩD0OD1OD2OD3O18AD9235

RP5 22ΩD0D1D2D3D8OD9OD10OD11O18D8D9D10D11RP3 22Ω27RP5 22Ω27RP3 22Ω36RP5 22Ω36RP3 22Ω45RP5 22Ω45RP4 22ΩD4OD5OD6O18RP6 22ΩD4D5D618RP4 22Ω27RP6 22Ω27RP4 22Ω36RP6 22Ω36RP4 22ΩD7O45RP6 22ΩWHTTP5OTRJP23JP22DUTAVDDD7OTRO45DUTAVDDINTB12AGNDTB13C58+22µF25V2FBEADL1TP2RED1R310kΩC570.1µFJP25JP24C22+10µF10VC360.1µFC390.001µFJP12DUTAVDDC590.1µFR410kΩC21+10µF10VAD9235C350.1µFWHTTP17783AVDDAGNDSENSEVREFPDWNREFBREFTMODEVIN+VIN–AGNDAVDDDGNDDRVDDU1OTR1D1128D1027D926D825D722D621D520OTROD0OD1OD2OD3OD4OD5OD6OD7OD8OD9OD10OD11ODUTCLKWHTTP6AVDDINTB11C47+22µF25V2FBEADL2TP1RED1C340.1µFAVDD4145C520.1µFC2010µF+10VC330.1µFC320.1µF6SHEET 3C500.1µF2VIN+VIN–9101112D419D318D217D116D015CLK13JP13AVDDTP3RED1AVDDR275kΩJP11DUTDRVDDR201kΩJP7JP62324DRVDDINTB15AGNDTB14C48+22µF25V2FBEADL3C530.1µFR171kΩR421kΩJP1DUTAVDDC23+10µF10VC380.1µFC410.001µFDUTDRVDDC1+10µF10VC370.1µFC400.001µFJP2DVDDINTB16C6+22µF25V2FBEADL4TP4RED1DVDDTP9BLKTP10BLKTP15BLKTP16BLK02461-044C140.1µFTP11BLKTP12BLKTP13BLKTP14BLK

Figure 44. TSSOP Evaluation Board Schematic, DUT

Rev. D | Page 21 of 40

AD9235

DVDDC120.1µFR2510kΩ6Data Sheet

AUXCLKS512AVDD1C410µF10V219234+112468T1–1T123R1149.9Ω541N5712T2MC100LVEL33D81VCCU3NC765D2D11N5712D0D1D2D3D4D5D6D7G1G2A1A2A3A5A6A7A8C110.1µFC510µF10V+21VCCGNDY1Y2201018171635AVDDOUTREFVEEINAINBINCOMAVDD234R2610kΩY3U6515A474VHC541Y467111315171921232527293133HEADER RIGHT ANGLE MALE NO EJECTORSRP2 22Ω16DD02RP2 22Ω15DD13RP2 22Ω14DD217910121416182022242628303234363840Y5Y6Y7Y814131211RP2 22Ω13DD3Ω12DD4RP2 2256RP2 22Ω11DD54AVDDAVDDR12113ΩR1490ΩC270.1µFR13113ΩR1590ΩC240.1µFU8 DECOUPLINGC260.1µF+C2810µF10VRP2 22Ω10DD6Ω9DD7RP2 2281RP2 22Ω16DD87RP2 22Ω15DD9Ω14DD10RP2 2234RP2 22Ω13DD112562010181716RP2 22Ω12RP2 22Ω11DOTR1JP9D8R19500ΩCLOCKS11219234G1G2A1A2A3A5A6A7A8VCCGNDY1Y27RP2 22Ω108RP2 22Ω9DACLK353739R210ΩCWC130.1µFR149.9ΩD10AVDD; 14AVDDAVDD; 7D11R7WHTU8U822ΩDUTCLKTP7OTR562174VHC0474VHC04JP4U834R18500ΩD9Y3U751574VHC541Y4A467HDR40RAMJ1Y5Y6Y7Y814131211JP3R922Ω74VHC04U874VHC04U8101213AVDDC100.1µFU9 DECOUPLINGC810µF10V11974VHC04802461-045U8

Figure 45. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering

Rev. D | Page 22 of 40

Data Sheet

JP5SINGLE INPUTS31AD9235

C70.1µFAVDDR231kΩR549.9ΩAVDDC1510µF10V122C90.33µFR411kΩJP42JP40JP45R2122ΩC4415pFVIN+AVDDC690.1µFC2VALR37499ΩR34523ΩAMP INPUTS212R321kΩJP46C42VALJP41JP43R2222ΩC44BR331kΩC80.1µFR0ΩVIN–C4315pF–IN13VCC4VO+R35499ΩR3149.9Ω+INAD8138U28625VO–VOCR1040ΩC45VALVEEC180.1µFC1910µF10V22ABR399ΩXFMR INPUTALT VEETP8RED3AVDD12+1C17VALS46T1–1T123R161kΩR2449.9Ω54T202461-0461JP8R81kΩC250.33µFC160.1µF

Figure 46. TSSOP Evaluation Board Schematic, Analog Inputs

DACLKAD9762DD0DD1DD2DD3DD4DD5DD6DD7DD8DD9DD10DD1112345671011121314U4MSB-DB11CLOCK28DB10DB19DB8DB7DB6DB5DB4DB3DB2DB1DB0NC1NC2DVDD27DCOM26NC325AVDD24COMP223IOUTA22IOUTB21ACOM20COMP119FSADJ18REFIO17REFLO16SLEEP15C300.1µFC310.01µFDVDDC290.1µFC460.01µFWHTTP18S6C560.1µFR2949.9ΩC5522pFR2849.9Ω02461-047C490.1µFR302kΩC510.1µFC5422pF

Figure 47. TSSOP Evaluation Board Schematic, Optional DAC

Rev. D | Page 23 of 40

Figure 48. TSSOP Evaluation Board Layout, Primary Side

Rev. D | Page 24 of 40

Data Sheet

AD9235

02461-048Data Sheet

AD9235

02461-049

Figure 49. TSSOP Evaluation Board Layout, Secondary Side

Rev. D | Page 25 of 40

AD9235

Data Sheet

02461-050

Figure 50. TSSOP Evaluation Board Layout, Ground Plane

Rev. D | Page 26 of 40

Data Sheet

_AD9235

02461-051

Figure 51. TSSOP Evaluation Board Power Plane

Rev. D | Page 27 of 40

AD9235

Data Sheet

02461-052

Figure 52. TSSOP Evaluation Board Layout, Primary Silkscreen

Rev. D | Page 28 of 40

Data Sheet

AD9235

02461-053

Figure 53. TSSOP Evaluation Board Layout, Secondary Silkscreen

Rev. D | Page 29 of 40

AD9235

EXTREF1V MAX E1R110kΩR910kΩC120.1µFP7AGNDAVDDP9BEP8CP10GNDGNDC2910µFP11DC130.10µFGNDC2210µFData Sheet

GNDAVDDP6R51kΩC110.1µFP1R71kΩP3R61kΩGNDP41123456H1GNDMTHOLE6P22.5VDRVDDMODEC80.1µFGNDVAMPAVDDH2MTHOLE6H3MTHOLE6H4MTHOLE6+3.0V2.5VC70.1µFGND3OVERRANGE BIT4(MSB)5.0V12345678GNDGNDGNDVDLC90.10µF22P52423222120191817C60.1µFR420ΩAMPINAVDDR361kΩR261kΩ25REFBDRVDD16DGND15D714GNDAVDDGNDVIN+26272829303132REFTAVDDAGNDVIN+VIN–AGNDPDWNDRVDDGND161514131211109DRXD13XD12XD11XD10XD9XD8XD7XVREFSENSEMODEOTRD11D10D9D8XOUTC150.1µFL110nHAMPGNDT1ADT 1–1 WTXFRIN11NC53624AD9235U4D613D512D411D310D2912345(LSB)678RP2 220ΩJ1R1036ΩR120ΩC2610pFC5GND0.1µFR433kΩC2110pFGNDVIN–GNDAVDDDNCDNCDNCPRISECGNDOPTIONAL XFRT2FT C1–1–13C160.1µFGNDR1136ΩXOUTBR2XXC1915pFDNCCLKCTE 45AVDDOR L1FOR FILTER12345678161514131211109D6XD5XD4XD3XD2XD1XD0XD0D1RP1 220ΩGNDR30ΩGNDC2310pFCLKR81kΩP14AVDDP13GNDSENSE PIN SOLDERABLE JUMPERE TO A EXTERNAL VOLTAGE DIVIDERE TO B INTERNAL 1V REFERENCE (DEFAULT)E TO C EXTERNAL REFERENCEE TO D INTERNAL 0.5V REFERENCEMODE PIN SOLDERABLE JUMPER5 TO 1 TWOS COMPLEMENT/DCS OFF02461-054X FRIN13524PRISECGNDXOUTCTXOUTBAMPINBC180.1µFR1533ΩAVDDR131kΩR251kΩGNDR18R SINGLE ENDED25ΩR3, R17, R18ONLY ONE SHOULD BEON BOARD AT A TIMEGND5 TO 2 TWOS COMPLEMENT/DCS OFF5 TO 3 OFFSET BINARY/DCS ON5 TO 4 OFFSET BINARY/DCS OFF

Figure 54. LFCSP Evaluation Board Schematic, Analog Inputs and DUT

Rev. D | Page 30 of 40

Data Sheet

CLKAT/DACMSBDRXD13XGNDD12XD11XDRVDDD10XD9XGNDD8XD7XD6XD5XGNDD4XD3XDRVDDD2XD1XGNDLSBD0X25262728293031323334353637383940414243444547AD9235

74LVTH162374U12OE242QB232Q7222CLK2DB2D7GND2D62D5VCC2D42D3GND2D22D11D81D7GND1D61D5VCC1D41D3GND1D21D11CLKINGNDDRY2HEADER 40GND2468101214161820222426283032343638401133557799111113131515171719192121232325252727292931313333353537373939GNDDR46810121416GND212Q6202Q52Q4GND2Q11Q719GNDMSBDRVDDGNDVCC18172Q316152Q21413GND18202224261Q81211GND101Q691Q51Q4GND1Q118GND2830VCC76DRVDDDRYGNDGNDGND32343638401Q3541Q232CLKLAT/DAC481OE1OUTVAMPR381kΩC440.1µFR391kΩGNDC2410µF+VAMPPOWER DOWNUSE R40 OR R41VAMPR4110kΩR4110kΩGNDGNDR4010kΩPWDNAMP INAMPC280.1µFRGP1INHIINLOR1950ΩGNDR3525ΩGNDC350.10µFR3325ΩRPG212345C45GND0.1µFR1425ΩAD8351U3109876VOCMVPOSOPH1OPLOCOMMGNDGNDR160ΩC270.1µFAMPINBAMPINC170.1µF02461-055R170ΩR341.2kΩ

Figure 55. LFCSP Evaluation Board Schematic, Digital Path

Rev. D | Page 31 of 40

C370.1µFC400.001µFC4610µFAD9235

Data Sheet

+0F2µC01+LPDFDVµNM1GA90V40C.0GFNIµS1S8040AC.0PYBF 7µH41CC.0TALFµ11C.0Fµ19030C.0Fµ18030C.0F6µ31C.0F4µ31C.0F1µ31C.0FGµNI1S00S30C.0APYB LFA2µTIC22G+IDDDFDV1µNR41GDC.0Fµ14010C.0F3µ31C.G0NIFSµS1A20P30YC.0B G5FO2µLC01ANADDDVF3µNDAC0G1D+GVNAFIµSD40SDC1DAV+NPRD0FGYB 1µLC2T2UD+DVPUTDENSAR22Ω DR0Y7A3LR DEDPNDNxN GEARD T2A2GR 7 OE3ΩWVR52TO SM)ECWR0ΩAO DY=/H SAxTLRA (CE KIxLTD RCAE MNHEOC HRACOTT3SFA2ΩR0XCDLNNDEGV36147811DRNGWP68XYYYYC1234V47ABABABAB1122334412459023111DDDDNNNN2G01C3Ω2ΩG2ΩG42ΩG1k3k54kN5R15R13Rk14R1EEEEE02135534EEEE8K2LLLLS7LDDDDTR 2CVVVVNER ESEMU STEUSD EUO10JD3Ωk3ΩDCOLR1Rk1DANCDN EN VGGDENE IRT87MECE2Ω2ΩITFR0R0 KFRI3FCUD4µOB AC1.0LA RXCROCCOFNNEFE92ΩR05DNGEDODCNNG65E20-J120

Figure 56. LFCSP Evaluation Board Schematic, Clock Input

Rev. D | Page 32 of 40

Data Sheet

750-120

Figure 57. LFCSP Evaluation Board Layout, Primary Side

850-120

Figure 58. LFCSP Evaluation Board Layout, Secondary Side Rev. D | Page 33 of 40

AD9235

950-120

Figure 59. LFCSP Evaluation Board Layout, Ground Plane

060-120

Figure 60. LFCSP Evaluation Board Layout, Power Plane

AD9235

160-120

Figure 61. LFCSP Evaluation Board Layout, Primary Silkscreen

Data Sheet

260-120

Figure 62. LFCSP Evaluation Board Layout, Secondary Silkscreen

Rev. D | Page 34 of 40

Data Sheet

AD9235

Package 0603

Value 0.1 µF

Recommended Vendor/ Supplied Part Number by ADI

Table 9. LFCSP Evaluation Board Bill of Materials (BOM)

Item Qty. Omit Reference Designator Device

1 18 C1, C5, C7, C8, C9, C11, Chip Capacitor

C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47

8 C6, C18, C27, C17,

C28, C35, C45, C44

2 8 C2, C3, C4, C10, C20, Tantalum Capacitor

C22, C25, C29

2 C46, C24 3 8 C14, C30, C32, C38, Chip Capacitor

C39, C40, C48, C49

4 3 C19, C21, C23 Chip Capacitor 5 1 C26 Chip Capacitor 6 9 E31, E35, E43, E44, Header

E50, E51, E52, E53

2 E1, E45 7 2 J1, J2 SMA Connector/50 Ω 8 1 L1 Inductor

TAJD 10 µF

0603 0603

0603 EHOLE

0.001 µF 10 pF 10 pF

Jumper Blocks

SMA 0603 TB6

10 nH

9 10 11 12 13

1 1 5 2 14

P12

R3, R12, R23, R28, RX

R37, R22, R42, R16, R17, R27 R4, R15

R5, R6, R7, R8, R13, R20, R21, R24, R25, R26, R30, R31, R32, R36 R10, R11 R29 R19

RP1, RP2 T1 U1

U4 U5 PCB U3 T2

R9, R1, R2, R38, R39 R18, R14, R35 R40, R41 R34 R33

Terminal Block

Header Dual 20-Pin RT Angle HEADER40 Chip Resistor 0603 0 Ω Chip Resistor Chip Resistor

0603 0603

33 Ω 1 k Ω

Coilcraft/

0603CS-10NXGBU

Wieland/25.602.2653.0, z5-530-0625-0

Digi-Key S2131-20-ND

14 15 16 17 18

2 1 2 1 1

1 1 1 5 3 2 1 1 34

Chip Resistor Chip Resistor Resistor Pack

ADT1-1WT 74LVTH162374 CMOS Register

AD9235BCP ADC (DUT) 74VCX86M

AD92XXBCP/PCB AD8351 Op Amp MACOM Transformer Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor

0603 0603 R_742

36 Ω 50 Ω 220 Ω

Digi-Key

CTS/742C163220JTR Mini-Circuits

Analog Devices, Inc. Fairchild

Analog Devices, Inc. Analog Devices, Inc. M/A-COM/ETC1-1-13

X X X

AWT1-1T TSSOP-48 LFCSP-32 SOIC-14 PCB MSOP-8 ETC1-1-13 0603 0603 0603

1-1 TX SELECT 25 Ω 10 k Ω 1.2 k Ω 100 Ω

19 1 20 1 21 1 22 23 24 25 26 27 28 Total 82

These items are included in the PCB design but are omitted at assembly.

Rev. D | Page 35 of 40

AD9235

Data Sheet

9.809.709.60OUTLINE DIMENSIONS

28154.504.404.301146.40 BSCPIN 10.65BSC0.150.05COPLANARITY0.100.300.191.20 MAX8°0°0.750.600.45SEATINGPLANE0.200.09COMPLIANT TO JEDEC STANDARDS MO-153-AE

Figure 63. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

5.105.00 SQ4.900.300.250.1825321EXPOSEDPADPIN 1INDICATORPIN 1INDICATOR0.50BSC243.253.10 SQ2.9517TOP VIEW0.800.750.700.500.400.3016BOTTOM VIEW0.25 MINSEATINGPLANE0.05 MAX0.02 NOMCOPLANARITY0.080.20 REFFOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.112408-A

Figure . 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 × 5 mm Body, Very Very Thin Quad

(CP-32-7)

Dimensions shown in millimeters

Rev. D | Page 36 of 40

Data Sheet

AD9235

Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C

Package Description

28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ)

Package Option RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 CP-32-7 CP-32-7 CP-32-7 CP-32-7 CP-32-7 CP-32-7

ORDERING GUIDE

Model1, 2

AD9235BRU-20 AD9235BRURL7-20 AD9235BRUZ-20 AD9235BRUZRL7-20 AD9235BRU-40 AD9235BRURL7-40 AD9235BRUZ-40 AD9235BRUZRL7-40 AD9235BRU-65 AD9235BRURL7-65 AD9235BRUZ-65 AD9235BRUZRL7-65 AD9235BCPZ-20

AD9235BCPZRL7-20 AD9235BCPZ-40 AD9235BCPZRL7-40 AD9235BCPZ-65 AD9235BCPZRL7-65

Z = RoHS Compliant Part.

It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board.

Rev. D | Page 37 of 40

AD9235

Data Sheet

NOTES

Rev. D | Page 38 of 40

Data Sheet

AD9235

NOTES

Rev. D | Page 39 of 40

AD9235

NOTES

Rev. D | Page 40 of 40

Data Sheet

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