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专利名称：Semiconductor device with capacitor and
fuse and its manufacture method
发明人：Masayoshi Omura申请号：US11797483申请日：20070503公开号：US07781280B2公开日：20100824
专利附图：
摘要：An upper electrode of a capacitor has a two-layer structure of first and secondupper electrodes. A gate electrode of a MOS field effect transistor and a fuse areformed by patterning conductive layers used to form the lower electrode, first upper
electrode and second upper electrode of the capacitor. In forming a capacitor and a fuseon a semiconductor substrate by a conventional method, at least three etching masks areselectively used to pattern respective layers to form the capacitor and fuse before wiringconnection. The number of etching masks can be reduced in manufacturing a
semiconductor device having capacitors, fuses and MOS field effect transistors so thatthe number of processes can be reduced and it becomes easy to improve theproductivity and reduce the manufacture cost.
申请人：Masayoshi Omura
地址：Hamamatsu JP
国籍：JP
代理机构：Dickstein Shapiro LLP
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