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专利名称：FPGA Simulated Annealing Accelerator发明人：Jonathan D. Phillips,Aravind Dasu申请号：US124260申请日：20090622
公开号：US20090319253A1公开日：20091224
专利附图：
摘要：Iterative repair problems are generally solved using a combinatorial searchmethod such as simulated annealing are addressed with a FPGA-based coarse-grainpipelined architecture to accelerate a simulated annealing based iterative repair-typeevent scheduling application. Over 99% of the work done by any simulated annealing
algorithm is the repeated execution of three high-level steps: (1) generating, (2)evaluating, and (3) determining the acceptability of a new problem solution. A pipelinedprocessor is designed to take advantage of these steps.
申请人：Jonathan D. Phillips,Aravind Dasu
地址：Logan UT US,Providence UT US
国籍：US,US
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