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专利名称：Read assist circuit for an SRAM, including a
word line suppression circuit
发明人：Lakshmikantha V. Holla,Vinod J.
Menezes,Theodore W. Houston,MichaelPatrick Clinton
申请号：US14271765申请日：20140507公开号：US09082507B2公开日：20150714
专利附图：
摘要：A memory circuit includes a bit cell that receives a word line, complementary bit
lines and an array supply voltage; a word line driver coupled to the word line, the wordline driver receiving the array supply voltage; and a word line suppression circuit coupledto the word line. The word line suppression circuit includes a diode and a first switchcoupled in series and a second switch. The switches are responsive to a control signal.The word line suppression circuit limits a word line voltage to a value lower than thearray supply voltage such that the static noise margin (SNM) of the bit cell is increased.
申请人：Texas Instruments Incorporated
地址：Dallas TX US
国籍：US
代理人：John R. Pessetto,Charles A. Brill,Frank D. Cimino
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