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专利名称：Data interface and high-speed
communication using the same
发明人：YAMAKAWA, SHIGEKI,GOKAN,
HIROSHI,OHTSUJI, AKIO
申请号：EP97954866申请日：19971027公开号：EP0955590A4公开日：20011205
摘要：A data interface for transferring data between processors which is formed ofwrite registers (12) in which the data from a data sending write processor are written inaccordance with a clock signal, read registers (13) in which the data written in these writeregisters are transferred by a later clock action and written, and from which the data areread out by a data receiving read processor, a write control means (15, 14-1 to 14-n) forwriting data selectively in a register among the write registers in accordance with anaddress signal and a write signal from the write processor, and a read control means (16,17) for reading data selectively from a register among the read registers in accordancewith an address signal from the read processor. Owing to a double buffer structure in thewrite registers and read registers, address and data signals are connected separately onthe write side and read side, so that the transfer of data can be carried out with theprocessors not interfering with each other.
申请人：MITSUBISHI DENKI KABUSHIKI KAISHA
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