RTC6715-DST-001

RTC6715

Data Sheet

SEP 2007 RTC6715-DST-001

RTC6715 CMOS 5.8GHz Band FM Receiver

Product Description

The RTC6715 is a highly integrated FM receiver intended for application on 5.8GHz band FM demodulation. This chip includes a low noise amplifier, mixer, IF amplifier, FM demodulator, AGC, audio demodulators, audio Amps and noise squelch. With RSSI voltage output, the instantaneous radio signal strength can be monitoring. RTC6715 is able to demodulate the FM modulated video and Stereo audio signals sourced from RTC6705 and separate the desired signal at the dedicated output pins. Both Stereo and Mono application are available on the chip. RTC6715’s operation frequency can be set by SPI programming, or by selecting six dedicated pins. Both CE and FCC regulations are easy to pass by using RTC6715 with application circuit and single room shielding case.

Features

󰁺 Single 3.3V supply power

󰁺 5.8GHz band FM demodulator with two audio subcarrier demodulators at 6MHz/6.5MHz 󰁺 High sensitivity -85dBm

󰁺 Simple six digital pins setting 24 fixed channels to eliminate external micro-controller 󰁺 Radio Strength Indicator (RSSI) 󰁺 Hard mute by noise squelch

󰁺 CMOS technology Single chip with integrated VCO and PLL 󰁺 48-pin Leadless QFN package pass RoHS

Application

󰁺 AV Sender 󰁺 Surveillance 󰁺 Baby Monitor 󰁺 Wireless Camera 󰁺 Wireless Audio 󰁺 Wireless Earphone

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RTC6715

Data Sheet

SEP 2007 RTC6715-DST-001

Block Diagram

VDD480VCOVDDVAMPVAMPOUTVDDIFARFGNDVDDCIFOUTS48474544434241403938VDDLNA51RFIN_5G2RFGND3SPIDATA//CS04VDD13736VDDNCNCNCLNA5G_LNAIFABFIFABFVCOFMDemo35VAMPIN34BBOUT2AGC6.5AudioDemo&Amp33VDDCP_6532FMIN_6531VDD33_6530VT_6529AUIN_656.0AudioDemo&Amp28AUOUT_6527FMIN_626AUOUT625AUIN_6SPILE/CS15SPICLK/CS26VCOVCOSPI_SE7BX8FSKCompDemodulationBufferAGCVDDESD9XTAL110XTAL211VDDSYN12SPISynthesizeSynthesizerrLoop Filter131415161718192021222324VDDRFVCOVDD3D3IFPDC_CVDDIFREG1D8VDDBSAGC_C

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VDDCP_6VDD33_6VT_6IFINNC

RTC6715

Data Sheet

SEP 2007 RTC6715-DST-001

Pin Descriptions

PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

NAME VDDLNA5 RFIN_5G RFGND CS0

SPIDATA CS1 SPILE CS2 SPICLK SPI_SE BX

VDDESD XTAL1 XTAL2 VDDSYN NC VDDRFVCO VDD3D3 REG1D8 VDDBS IFPDC_C VDDIF IFIN AGC_C VDDCP_6 VDD33_6 VT_6 AUIN_6 AUOUT6 FMIN_6 AUOUT_65 AUIN_65 VT_65 VDD33_65 FMIN_65 VDDCP_65 BBOUT2 VAMPIN NC VDD1 NC

VAMPOUT VDDVAMP VDD480VCO

I/O

Supply In Analog In Analog GND Digital In Digital In Digital In Digital In Digital In Digital In Digital In Digital In Supply In Analog In Analog In

Digital Ground Supply In Supply In Analog Out Supply In Analog Out Supply In Analog In Analog I/O Supply In Supply In Analog Out Analog IN Analog Out Analog In Analog Out Analog In Analog Out Supply In Analog In Digital In Analog Out Analog In

Supply In

Analog Out Supply In Supply In

FUNCTION

3.3V for RX LNA5G

5 GHz LNA input for RF input signal RF ground

Easy channel selection (Internal pull high) 1 SPI bus data input1

Easy channel selection (Internal pull high) 1 SPI bus latch enable input1

Easy channel selection (Internal pull high) 1 SPI bus clock input1

Switch mode or SPI selection 1

At easy channel selection mode : BX is used for alternative band selection 1

At SPI mode : BX is Don’t care 3.3V

Crystal Input Crystal Input

3.3V for RF synthesizer Not connected 3.3V for 5GHz VCO

3.3V for digital 1.8V regulator Regulator 1.8V for Digital block 3.3V for Bias RSSI Out

3.3V for IFAAF IFA_AF inputs

AGC Rectifier output

3.3V for 6MHz charge pump and VCO 3.3V for 6MHz audio amplifier Audio demo out for 6MHz VCO Audio amplifier in for 6MHz path Audio amplifier out for 6MHz path 6MHz FM audio in

Audio amplifier out for 6.5MHz path Audio amplifier in for 6.5MHz path Audio demo out for 6.5MHz VCO 3.3V for 6.5MHz audio amplifier 6.5MHz FM audio in

3.3V for 6.5MHz charge pump and VCO FMDeMod Buffer output Video amp input Not connected 3.3V

Not connected Video amp output 3.3V for Video Amp

3.3V for FM demod VCO

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RTC6715

Data Sheet

SEP 2007 RTC6715-DST-001

Pin Descriptions (continued)

PIN 42 43 44 45 46 47 NAME VDDIFA IFOUT VDD NC RFGND NC I/O

Supply In Analog Out Supply In

Analog GND Digital In

FUNCTION

3.3V for RX IFAs IF OUT 3.3V VDD Not connected RF ground Not connected A/B band selection 1

0 for A band; 1 for B band

48 S

Note 1. Digital pins, BX, SPI_SE and SPIDATA/CS0, SPILE/CS1 and SPICLK/CS2 are internal pull-high circuits.

Electrical Specification

(1) Absolute Maximum Ratings

SYMBOL

PARAMETER

Ratings

UNIT

Tstr Totr Vdd Vlog

VRX Storage Temperature Range Operating Temperature Range

Supply Voltage Logic control signal

RX input -65 to +150 -40 to +85 -0.5 to +5 -0.5 to +5 -2 to +2 °C °C V V V

The maximum rating must not be exceeded at any time. Do not operate the device under conditions outside the above

(2) DC Electrical Characteristics

SYMBOL Tj VDD33 I_module Icc Fref V_IH V_IL

PARAMETER

Temperature Range 3.3V Supply Voltage Power consumption under test circuit and color-bar test pattern

Power consumption

Oscillator operating frequency High Level Input Voltage for Digital

Interface

Low Level Input Voltage for Digital

Interface

CONDITION

TT 25C, 3.3V TT 25C, 3.3V

V_IO=3V

MIN. -40 3.1 0.7xV_IO -0.3

TYP. 25 3.3 195 146 8

MAX. 85 3.5 V_IO+0.3 0.3xV_IO

UNIT °C V mA mA MHz V V

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RTC6715

Data Sheet

SEP 2007 RTC6715-DST-001

(3) 5GHz Band FM Receiver Specifications (VDD=+3.3V, 25℃)

SYMBOL

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNIT

RF_Freq IF_Freq S11 Si

RF Input frequency IF output frequency RF Input return loss under

test circuit Input Sensitivity measurement under test

circuit

External matching@50Ω SNR 43dB Fmod=15KHz Frequency deviation :±2.5MHz LPF BW:20KHz 100KHz offset 1MHz offset -91dBm 5dBm

SE SE CONDITION 75ohm load

Fmod: 1KHz tone Frequency deviation:

±25Khz Load: > 1Kohm Fmod: 1KHz tone Frequency deviation:

±50Khz Load: > 1Kohm Fmod: 1KHz tone Frequency deviation:

±25Khz Load: > 1Kohm Fmod: 1KHz tone with 2Vpp audio output

Load: > 1Kohm

5725 479

480 -10

5865

MHz MHz dB

-85 dBm

Phase noise VRSSI Z22_IFout Z22_IFin SYMBOL Video

V_pp Audio

Carrier_Freq Output signal level

LO: 5246MHz RSSI output voltage IF 480MHz output

Impedance IF 480MHz Input Impedance PARAMETER Vpp after video clamping Audio carrier frequency

Vpp after Audio Amplifier

MIN.

-90 -112 0.5~1.1 50 50 TYP. 1 6/6.5 1

MAX.

dBc/Hz V Ω Ω UNIT Vpp MHz Vpp

Max_App

Maxmum Vpp after Audio amplifier with distortion <1% Total harmonic distortion Output 1Vpp (1KHz

tone) Audio SNR (as reference

design,) With pre-emphasis/ de-emphasis

2 Vpp

THD 1% %

S/N 56 dB

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RTC6715

Data Sheet

SEP 2007 RTC6715-DST-001

(4) SPI Digital Timing Diagram

In SPI Mode (SPI_SE = 1), the 3-wire SPI interface is used to configure the frequency as well as internal registers. Series data sequence of 3-wire SPI is shown in following Figure. This 25-bit data stream consists of 4 address bits, 1 read/write control bit and 20 data bits. Data transfer is LSB first.

During write cycle (R/W = 1), the chip will sample the SPIDATA on the rising edge of SPICLK. Sampled data will be temporally stored in internal shift register. One the rising edge of SPILE, data in shift register will be latched into specific register according to the address.

During read cycle (R/W = 0), address and read/write control bit are sampled at rising edge of SPICLK, but the data bits are sent at the falling edge of SPICLK. LSB1st dataMSBInvalid Data2nd dataSPIDATAA0A1A2A3R/WD0D1D18D19SPICLKt 1t 2t 3t 6SPILEt 7tt 4t 5

Figure 6.1 Series data sequence on SPI interface of RTC6716

Parameter

t1 t2 t3 t4 t5 t6 t7

Note:

1.) On the rising edge of the SPICLK, one bit of data is transferred into the shift register. 2.) SPILE should be “L” when the data is transferred into the shift register.

Min. 20 20 30 30 100 20 100

Typ. - - - - - - -

Max. - - - - - - -

Unit ns ns ns ns ns ns ns

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RTC6715

Data Sheet

SEP 2007 RTC6715-DST-001

Channel Selection Table When pin 7 (SPI_SE) is set at low voltage, the chip works as in the easy channel selection mode and the pins 4(SPIDATA/CS0), 5(SPILE/CS1), 6(SPICLK/CS2)，48(S) and 8(BX) are used for channel selection. Channel frequencies refer to below table. SPI_SE5GHzBand0001BandABESPI BX001XS01XX0005865M5733M5705M0015845M5752M5685MCS[2:0]0100111001015825M5805M5785M5765M5771M5790M5809M5828M5665M55M5885M5905Mthree wire SPI control pins1105745M5847M5925M1115725M5866M5945M SPI mode

When pin 7 (SPI_SE) is set at high (3.3V), the chip works as in the SPI mode and the pins 4(SPIDATA/CS0), 5(SPILE/CS1) and 6(SPICLK/CS2) are used for ‘SPI’ inputs for 3-wire programming

Address 0x00: Synthesizer Register A

Bits Name 5G Default

0

0 19

18

17 － 0

0

0

0

0

0

0

0

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SYN_RF_R_REG [14:0] 0

0

0

0

0

0

1

0

0

0

SYN_RF_R_REG [14:0]:

Default

5.8GHz: 0010H

R-counter divider ratio control for RF Synthesizer. For 5.8GHz Default: 00008H Crystal clock (Fosc )=: 8MHz

Reference clock=crystal clock/R-counter=8MHz/8=1MHz

Address 0x01: Synthesizer Register B

Bits Name 5G Default

0

0

0

0

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SYN_RF_N_REG [12:0] 0

0

1

0

1

0

1

0

0

0

SYN_RF_A_REG [6:0] 0

0

0

1

0

1

Default

5.8GHz: 02A05H

Synthesizer counter default setting ( 5.8Ghz band:5865MHz) For 5.8Ghz band, FLO = 2*(N*32+A)*(Fosc/R)

Example: default FRF=5865MHz, FLO=5865-479=5386MHz, Fosc=8MHz, R=8 5385/2=(N*32+A)*8Mhz/8=2*(N*32+A)*1MHz N=84(=1010100), A5(=0101) For 5.8GHz default: 02A05H SYN_RF_N_REG [12:0]: N counter divider ratio control for RF Synthesizer.

SYN_RF_A_REG [6:0]: A counter divider ratio control for RF Synthesizer.

Address 0x02: Synthesizer Register C

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RTC6715

Data Sheet

15

14

13

12

11

10

9

8

7 CP_FT [2:0] 0

0

1 6

5 SC_CTL 4

RTC6715-DST-001

Bits

19

18

17

16

SEP 2007 3

2

1

0

Name

AGC_6M [2:0] 1

1

0

AGC_6M5 [2:0] 1

1

0

CC_VCO [1:0] 1

1

CP_5GLO [2:0] 0

1

1

MOUT [1:0] 0

0

PRES_FT [2:0] 0

1

1

Default 0

Default: FFE44H AGC_6M [2:0] AGC_6M5 [2:0] CC_VCO [1:0] CP_5GLO [2:0] CP_FT [2:0] SC_CTL: MOUT [1:0] PRES_FT [2:0]

6M Audio Demodulator AGC control 6M5 Audio Demodulator AGC control VCO current control

5G VCO buffer current control

Charge pump current control (from 50uA to 6mA, default=100uA) CP current test control

Multi-function output select

(RF R divider output, RF prescaler output, lock in detect) Prescaler tail current control (20 ~ 140uA).

Address 0x03: Synthesizer Register D

Bits Name Default

0

0

0

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SYN_C3 [2:0]

0

0

0

1

1

1

SYN_CZ [2:0] 0

0

1

1

0

0

SYN_RZ [7:0] 0

0

0

0

0

－

Default: 03980H SYN_C3 [2:0]: SYN_CZ [2:0]: SYN_RZ [7:0]:

Loop filter C3 control Loop filter CZ control Loop filter RZ control

Address 0x04: VCO Switch-Cap Control Register

Bits Name Default

0 19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RFVCO_EX_CAP

[4:0] 0

0

1

1

1

VCO480_EX_CAP

[4:0] 1

0

0

0

0

VCO6M _EX_CAP

[4:0] 1

1

1

0

0

VCO6M5_EX_CAP

[4:0]

1

1

1

0

Default: 7ABEFH

RFVCO_EX_CAP [4:0]: 480VCO_EX_CAP [4:0]: 6MVCO_EX_CAP [4:0]: 6M5VCO_EX_CAP [4:0]:

For RF VCO adjustment For IF VCOadjustment For 6M VCOadjustment For 6M5 VCOadjustment

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RTC6715

Data Sheet

SEP 2007 RTC6715-DST-001

Address 0x05: DFC Control Register

Bits

19 EN_RECAL 18

17

16

15

14

13

12 OK_RF 11 OK_IF 10 OK_6M 9 OK_6M5 8

7

6

5

4

3

2

1

0

Name R [5:0]

VCODFC_OVP DFC480_OVP AUDFC_OVP

[2:0] [2:0] [2:0]

Default

0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 0

EN_RECAL:

R [5:0]: OK_RF: OK_IF: OK_6M: OK_6M5:

VCODFC_OVP [2:0]: DFC480_OVP [2:0]: AUDFC_OVP [2:0]:

DFC reference clock control, set default value to 63. RF VCO fine tune IF VCO fine tune 6M VCO fine tune 6M5 VCO fine tune RF VCO setting IF VCO setting

6M/6M5 VCO setting

Address 0x06: 6M Audio Demodulator Control Register

Bits Name Default

1

0 19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

6M_ICP [5:0]

0

0

0

0

6M_C3 [2:0] 1

0

0

6M_CZ [2:0] 1

0

0

0

0

0

6M_RZ [7:0] 0

1

0

0

0

Default: 82408H 6M_ICP [5:0]: 6M_C3 [2:0]: 6M_CZ [2:0]: 6M_RZ [7:0]:

6M Charge-Pump current control 6M Loop Filter Adjusting 6M Loop Filter Adjusting 6M Loop Filter Adjusting

Address 0x07: 6M5 Audio Demodulator Control Register

Bits Name Default

1 19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

6M5_ICP [5:0] 0

0

0

0

0

6M5_C3 [2:0] 6M5_CZ [2:0] 1

0

0

1

0

0

0

0

6M5_RZ [7:0] 0

0

1

0

0

0

Default: 82408H 6M5_ICP [5:0]: 6M5_C3 [2:0]: 6M5_CZ [2:0]: 6M5_RZ [7:0]:

6M5 Charge-Pump current control 6M5 Loop Filter Adjusting 6M5 Loop Filter Adjusting 6M5 Loop Filter Adjusting

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RTC6715

Data Sheet

SEP 2007 RTC6715-DST-001

Address 0x08: Receiver Control Register 1

Bits Name Default

0 19

18 － 0

0 17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CP_MIXER [2:0] 1

1

1

1

IFA_GN [2:0]

1

1

0

1

0

VAMP_GN [7:0] 0

0

0

0

0

Reserved 0

0

0

Default: 0FF80H CP_MIXER [2:0]: IFA_GN [2:0]: VAMP_GN [7:0]:

RF Mixer current control IFABF gain control

Video Amp gain control 2

Address 0x09: Receiver Control Register 2

Bits Name Default

19

18

17

16

15

14

13

12

11

10

9 BC [2:0] 0

0

0

0

0

8

7

6

5

4

3

2

1

0

IFAF_GN [2:0] 1

0

1

REGBS_VADJ REGIF_VADJ

[2:0] [2:0] 1

0

0

1

0

0

RSSI_SQUELCH_D

[7:0] 0

1

1

0

0

0

Default: B2007H IFAF_GN [2:0]:

REGBS_VADJ [2:0]: REGIF_VADJ [2:0]: BC [2:0]:

RSSI_SQUELCH_D [7:0]:

IFAAF gain control

BS regulator reference voltage adjust IF regulator reference voltage adjust BC adjust

RSSI & noise squelch control

Address 0x0A: Power Down Control Register

Bits

19

18

17 PD_IF_DEMOD 16

15 PD_RSSI_SQUELCH 14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PD_VCLAMP PD_REG1D8 Name

5G Default

0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1

Default:

5.8GHz: 10C13H PD_VCLAMP: Video clamp power down control PD_VAMP: Video amp power down control PD_IF_DEMOD: IF demodulator power down control PD_IFAF: IFAF power down control PD_RSSI_SQUELCH: RSSI & noise squelch power down control PD_REGBS: BS regulator power down control PD_REGIF: IF regulator power down control PD_BC: BC power down control PD_DIV4: Divide-by-4 power down control PD_5GVCO: 5G VCO power down control www.richwave.com.tw Specifications subject to change without notice Preliminary Confidential Proprietary Rev V0.2

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PD_PLL1D8 1

PD_REGBS PD_5GVCO PD_AU6M5 PD_MIXER PD_REGIF PD_IFABF PD_VAMP PD_AU6M PD_DIV80 PD_IFAF PD_DIV4 PD_SYN PD_6M5 PD_BC PD_6M

RTC6715

Data Sheet

SYN power down control

6M audio modulator power down control 6M power down control

6M5 audio modulator power down control 6M5 power down control

1.8V regulator power down control IFABF power down control RF Mixer power down control Divide-by-80 power down control

PLL 1.8V regulator power down control

RTC6715-DST-001

PD_SYN: PD_AU6M: PD_6M: PD_AU6M5: PD_6M5:

PD_REG1D8: PD_IFABF: PD_MIXER: PD_DIV80: PD_PLL1D8:

SEP 2007 Address 0x0B~0x0E: Reserved

Address 0x0F: State Register

Bits Name Default

0

0

0

0

0

0

0

0

19

18

17

16

15

14

13

12

11 － 0

0

0

0

0

0

0

0

0

0

10

9

8

7

6

5

4

3

2

1

0

STATE [2:0] 0

0

STATE [2:0]

000 001 010 011 100~111

State Name RESET PWRON_CAL

STBY VCO_CAL Reserved

Description

Reset state. Power on state. Standby state. VCO state.

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RTC6715-DST-001

Data Sheet

PACKAGE

QFN 7X7 48 pins

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RTC6715

SEP 2007

Preliminary Confidential Proprietary