uc2844bd(电源芯片)

Current Mode Controllers

The UC3844B, UC3845B series are high performance fixedfrequency current mode controllers. They are specifically designed forOff−Line and dc−dc converter applications offering the designer acost−effective solution with minimal external components. Theseintegrated circuits feature an oscillator, a temperature compensatedreference, high gain error amplifier, current sensing comparator, and ahigh current totem pole output ideally suited for driving a powerMOSFET.

Also included are protective features consisting of input andreference undervoltage lockouts each with hysteresis, cycle−by−cyclecurrent limiting, a latch for single pulse metering, and a flip−flopwhich blanks the output off every other oscillator cycle, allowingoutput deadtimes to be programmed from 50% to 70%.

These devices are available in an 8−pin dual−in−line and surfacemount (SOIC−8) plastic package as well as the 14−pin plastic surfacemount (SOIC−14). The SOIC−14 package has separate power andground pins for the totem pole output stage.

The UCX844B has UVLO thresholds of 16 V (on) and 10 V (off),ideally suited for off−line converters. The UCX845B is tailored forlower voltage applications having UVLO thresholds of 8.5 V (on) and7.6 V (off).

Features

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PDIP−8N SUFFIXCASE 626

8

1SOIC−8D1 SUFFIXCASE 751

14

1

SOIC−14D SUFFIXCASE 751A

PIN CONNECTIONS

CompensationVoltage FeedbackCurrent Sense

RT/CT

12348765•••••••••••

Pb−Free Packages are Available

Trimmed Oscillator for Precise Frequency ControlOscillator Frequency Guaranteed at 250 kHz

Current Mode Operation to 500 kHz Output Switching FrequencyOutput Deadtime Adjustable from 50% to 70%Automatic Feed Forward Compensation

Latching PWM for Cycle−By−Cycle Current LimitingInternally Trimmed Reference with Undervoltage LockoutHigh Current Totem Pole Output

Undervoltage Lockout with HysteresisLow Startup and Operating Current

(Top View)

CompensationNC

Voltage Feedback

NC

Current Sense

NCRT/CT

1234567141312111098VrefVCCOutputGND

VrefNCVCCVCOutputGND

Power Ground

(Top View)

ORDERING INFORMATION

See detailed ordering and shipping information in the packagedimensions section on page 2 of this data sheet.

DEVICE MARKING INFORMATION

See general marking information in the device markingsection on page 16 of this data sheet.

© Semiconductor Components Industries, LLC, 20041

September, 2004 − Rev. 3

Publication Order Number:

UC3844B/D

UC3844B, UC3845B, UC2844B, UC2845B

VCC7(12)Vref

8(14)RRVrefUndervoltageLockout5.0VReferenceVCCUndervoltageLockoutVC7(11)Output6(10)PowerGround5(8)CurrentSense Input

RT/CT

4(7)VoltageFeedback

InputOutput/Compensation

OscillatorLatchingPWM2(3)1(1)ErrorAmplifier3(5)GND5(9)Pin numbers in parenthesis are for the D suffix SOIC−14 package.

Figure 1. Simplified Block Diagram

ORDERING INFORMATION

DeviceUC384xBDUC384xBDR2UC3844BDR2GUC384xBD1UC3844BD1GTA = 0° to +70°CUC384xBD1R2UC384xBD1R2GUC384xBNUC384xBNGUC2845BDUC284xBDR2UC2845BDR2GUC2845BD1UC284xBD1R2UC284xBD1R2GUC2844BNUC384xBVDUC3844BVDR2UC384xBVD1UC384xBVD1R2UC384xBVNTA = −40° to +105°CTA = −25° to +85°COperatingTemperature RangePackageSOIC−14SOIC−14SOIC−14(Pb−Free)SOIC−8SOIC−8(Pb−Free)SOIC−8SOIC−8(Pb−Free)PDIP−8PDIP−8(Pb−Free)SOIC−14SOIC−14SOIC−14(Pb−Free)SOIC−8SOIC−8SOIC−8(Pb−Free)PDIP−8SOIC−14SOIC−14SOIC−8SOIC−8PDIP−8Shipping†55 Units/Rail2500 Tape & Reel2500 Tape & Reel98 Units/Rail98 Units/Rail2500 Tape & Reel2500 Tape & Reel50 Units/Rail50 Units/Rail55 Units/Rail2500 Tape & Reel2500 Tape & Reel98 Units/Rail2500 Tape & Reel2500 Tape & Reel50 Units/Rail55 Units/Rail2500 Tape & Reel98 Units/Rail2500 Tape & Reel50 Units/Rail†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

x indicates either a 4 or 5 to define specific device part numbers.

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UC3844B, UC3845B, UC2844B, UC2845B

MAXIMUM RATINGS

RatingTotal Power Supply and Zener CurrentOutput Current, Source or Sink (Note 1)Output Energy (Capacitive Load per Cycle)Current Sense and Voltage Feedback InputsError Amp Output Sink CurrentPower Dissipation and Thermal CharacteristicsD Suffix, Plastic Package, SOIC−14 Case 751AMaximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−AirD1 Suffix, Plastic Package, SOIC−8 Case 751Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−AirN Suffix, Plastic Package, Case 626Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−AirOperating Junction TemperatureOperating Ambient TemperatureUC3844B, UC3845BUC2844B, UC2845BStorage Temperature RangeSymbol(ICC + IZ)IOWVinIOValue301.05.0−0.3 to +5.510UnitmAAmJVmAPDRqJAPDRqJAPDRqJATJTA8621457021781.25100+1500 to +70−25 to +85−65 to +150mW°C/WmW°C/WW°C/W°C°CTstg°CMaximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limitvalues (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,damage may occur and reliability may be affected.

1.Maximum package power dissipation limits must be observed.

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values

TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)UC284XBCharacteristicREFERENCE SECTIONReference Output Voltage (IO = 1.0 mA, TJ = 25°C)Line Regulation (VCC = 12 V to 25 V)Load Regulation (IO = 1.0 mA to 20 mA)Temperature StabilityTotal Output Variation over Line, Load, and TemperatureOutput Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C)Long Term Stability (TA = 125°C for 1000 Hours)Output Short Circuit CurrentOSCILLATOR SECTIONFrequencyTJ = 25°CTA = Tlow to ThighTJ = 25°C (RT = 6.2 k, CT = 1.0 nF)Frequency Change with Voltage (VCC = 12 V to 25 V)Frequency Change with Temperature (TA = Tlow to Thigh)Oscillator Voltage Swing (Peak−to−Peak)Discharge Current (VOSC = 2.0 V)TJ = 25°CTA = Tlow to Thigh(UC284XB, UC384XB)TA = Tlow to Thigh(UC384XBV)fOSCkHz4948225−−−7.87.5−52−2500.21.01.68.3−−55562751.0−−8.88.8−4948225−−−7.87.67.252−2500.20.51.68.3−−55562751.0−−8.88.88.8%%VmAVrefReglineRegloadTSVrefVnSISC4.95−−−4.9−−−305.02.03.00.2−505.0−855.052025−5.1−−−1804.9−−−4.82−−−305.02.03.00.2−505.0−855.12025−5.18−−−180VmVmVmV/°CVmVmVmASymbolMinTypMaxUC384XB, XBVMinTypMaxUnitDfOSC/DVDfOSC/DTVOSCIdischg2.Adjust VCC above the Startup threshold before setting to 15 V.3.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.Tlow=0°C for UC3844B, UC3845BThigh=+70°C for UC3844B, UC3845B

=−25°C for UC2844B, UC2845B=+85°C for UC2844B, UC2845B=−40°C for UC3844BV, UC3845BV=+105°C for UC3844BV, UC3845BV

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UC3844B, UC3845B, UC2844B, UC2845B

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 4], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values

TA is the operating ambient temperature range that applies [Note 5], unless otherwise noted.)

UC284XBCharacteristicERROR AMPLIFIER SECTIONVoltage Feedback Input (VO = 2.5 V)Input Bias Current (VFB = 5.0 V)Open Loop Voltage Gain (VO = 2.0 V to 4.0 V)Unity Gain Bandwidth (TJ = 25°C)Power Supply Rejection Ratio (VCC = 12 V to 25 V)Output CurrentSink (VO = 1.1 V, VFB = 2.7 V)Source (VO = 5.0 V, VFB = 2.3 V)Output Voltage SwingHigh State (RL = 15 k to ground, VFB = 2.3 V)Low State (RL = 15 k to Vref, VFB = 2.7 V)(UC284XB, UC384XB)(UC384XBV)CURRENT SENSE SECTIONCurrent Sense Input Voltage Gain (Notes 6 & 7)(UC284XB, UC384XB)(UC384XBV)Maximum Current Sense Input Threshold (Note 6)(UC284XB, UC384XB)(UC384XBV)Power Supply Rejection Ratio(VCC = 12 V to 25 V) (Note 6)Input Bias CurrentPropagation Delay (Current Sense Input to Output)OUTPUT SECTIONOutput VoltageLow State(ISink = 20 mA)(ISink = 200 mA, UC284XB, UC384XB)(ISink = 200 mA, UC384XBV)High State(ISource = 20 mA, UC284XB, UC384XB)(ISource = 20 mA, UC384XBV)(ISource = 200 mA)Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA)Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C)Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C)UNDERVOLTAGE LOCKOUT SECTIONStartup ThresholdUCX844B, BVUCX845B, BVMinimum Operating Voltage After Turn−OnUCX844B, BVUCX845B, BVVthV157..07.0168.4107.6179.0118.214.57.88.57.0168.4107.617.59.0V11.58.2VVOLVOH−−−13−12−−−0.11.6−13.5−13.40.150500.42.2−−−−1.1150150−−−1312.912−−−0.11.61.613.5−13.40.150500.42.22.3−−−1.1150150VnsnsAVV/V2.85−0.9−−−−3.0−1.0−70−2.01503.15−1.1−−−103002.852.850.90.85−−−3.03.01.01.070−2.01503.153.25V1.11.1−−10300dBmAnsVFBIIBAVOLBWPSRRISinkISourceVOHVOL2.45−650.7602.0−0.55.0−−2.5−0.1901.07012−1.06.20.8−2.55−1.0−−−−−−1.1−2.42−650.7602.0−0.55.0−−2.5−0.1901.07012−1.06.20.80.82.58−2.0−−−−−V−1.11.2VmAdBMHzdBmASymbolMinTypMaxUC384XB, XBVMinTypMaxUnitVthPSRRIIBtPLH(In/Out)VOL(UVLO)trtfVCC(min)4.Adjust VCC above the Startup threshold before setting to 15 V.5.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

Thigh=+70°C for UC3844B, UC3845BTlow=0°C for UC3844B, UC3845B

=−25°C for UC2844B, UC2845B=+85°C for UC2844B, UC2845B=−40°C for UC3844BV, UC3845BV=+105°C for UC3844BV, UC3845BV

6.This parameter is measured at the latch trip point with VFB = 0 V.7.Comparator gain is defined as: AV =DV Output/CompensationDV Current Sense Inputhttp://onsemi.com

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UC3844B, UC3845B, UC2844B, UC2845B

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 8], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values

TA is the operating ambient temperature range that applies [Note 9], unless otherwise noted.)

UC284XBCharacteristicPWM SECTIONDuty CycleMaximum(UC284XB, UC384XB)Maximum(UC384XBV)MinimumTOTAL DEVICEPower Supply CurrentStartup(VCC = 6.5 V for UCX845B, Startup(VCC = 14 V for UCX844B, BV)Operating (Note 8)Power Supply Zener Voltage (ICC = 25 mA)ICCmA−−VZ300.312360.517−−−300.312360.517−V%DC(max)DC(min)47−−48−−50−04746−4848−50500SymbolMinTypMaxUC384XB, XBVMinTypMaxUnit8.Adjust VCC above the Startup threshold before setting to 15 V.9.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

Thigh=+70°C for UC3844B, UC3845BTlow=0°C for UC3844B, UC3845B

=−25°C for UC2844B, UC2845B=+85°C for UC2844B, UC2845B=−40°C for UC3844BV, UC3845BV=+105°C for UC3844BV, UC3845BV

8050RT, TIMING RESISTOR (kΩ)208.05.02.00.810 k

NOTE: Output switches at1/2 the oscillator frequency20 k

% DT, PERCENT OUTPUT DEADTIMEVCC = 15 VTA = 25°C75

706560

1.󰀄CT = 10 nF2.󰀄CT = 5.0 nF3.󰀄CT = 2.0 nF4.󰀄CT = 1.0 nF5.󰀄CT = 500 pF6.󰀄CT = 200 pF7.󰀄CT = 100 pF32147555010 k

5620 k

50 k100 k200 k500 k

fOSC, OSCILLATOR FREQUENCY (kHz)

1.0 M

50 k100 k200 k500 kfOSC, OSCILLATOR FREQUENCY (kHz)

1.0 M

Figure 2. Timing Resistorversus Oscillator FrequencyFigure 3. Output Deadtimeversus Oscillator Frequency

2.55 V

VCC = 15 VAV = −1.0TA = 25°C

3.0 V

VCC = 15 VAV = −1.0TA = 25°C

20 mV/DIV2.5 V2.5 V

2.45 V

0.5 ms/DIV

2.0 V

1.0 ms/DIV

Figure 4. Error Amp Small Signal

Transient ResponseFigure 5. Error Amp Large Signal

Transient Response

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200 mV/DIVUC3844B, UC3845B, UC2844B, UC2845B

AVOL, OPEN LOOP VOLTAGE GAIN (dB)100806040

Phase200−󰀃2010

100

1.0 k10 k100 kf, FREQUENCY (Hz)

1.0 M

GainVCC = 15 VVO = 2.0 V to 4.0 VRL = 100 kTA = 25°C0306090φ, EXCESS PHASE (DEGREES)Vth, CURRENT SENSE INPUT THRESHOLD (V)1.2

VCC = 15 V1.00.8

TA = 25°C0.60.4

TA = −󰀃55°C0.20

TA = 125°C12015018010 M

0

2.04.06.0VO, ERROR AMP OUTPUT VOLTAGE (VO)

8.0

Figure 6. Error Amp Open Loop Gain and

Phase versus FrequencyFigure 7. Current Sense Input Threshold

versus Error Amp Output Voltage

ISC, REFERENCE SHORT CIRCUIT CURRENT (mA)∆Vref, REFERENCE VOLTAGE CHANGE (mV)0

VCC = 15 V−󰀃4.0−󰀃8.0−󰀃12

TA = 125°C−󰀃16−󰀃20

TA = 25°C−󰀃24

0

20

406080100

Iref, REFERENCE SOURCE CURRENT (mA)

120

TA = −󰀂55°C110

VCC = 15 VRL ≤ 0.1 W90

70

50−󰀃55

−󰀃25

0255075TA, AMBIENT TEMPERATURE (°C)

100125

Figure 8. Reference Voltage Change

versus Source CurrentFigure 9. Reference Short Circuit Current

versus Temperature

∆V, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)VCC = 15 V

IO = 1.0 mA to 20 mATA = 25°C

∆V, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)VCC = 12 V to 25 VTA = 25°C

O2.0 ms/DIV

O2.0 ms/DIV

Figure 10. Reference Load RegulationFigure 11. Reference Line Regulation

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UC3844B, UC3845B, UC2844B, UC2845B

Vsat, OUTPUT SATURATION VOLTAGE (V)0−1.0−󰀃2.0VCCTA = 25°CSource Saturation(Load to Ground)VCC = 15 V80 ms Pulsed Load120 Hz Rate90

%

VCC = 15 VCL = 1.0 nFTA = 25°C

TA = −󰀃55°C3.02.01.000TA = −󰀃55°CTA = 25°CSink Saturation(Load to VCC)GND80010%

50 ns/DIV

200400600I󰀃O, OUTPUT LOAD CURRENT (mA)

VO, OUTPUT VOLTAGEFigure 12. Output Saturation Voltage

versus Load Current

VCC = 30 VCL = 15 pFTA = 25°C

25ICC, SUPPLY CURRENT (mA)20 V/DIV201510

UCX845BFigure 13. Output Waveform

ICC, SUPPLY CURRENT100 mA/DIV50

RT = 10 kCT = 3.3 nFVFB = 0 VISense = 0 VTA = 25°C010UCX844B100 ns/DIV

2030VCC, SUPPLY VOLTAGE (V)

40Figure 14. Output Cross ConductionFigure 15. Supply Current versus Supply Voltage

PIN FUNCTION DESCRIPTION

Pin8−Pin1234567810121481192,4,6,1314−Pin1357FunctionCompensationVoltage FeedbackCurrent SenseRT/CTGNDOutputVCCVrefPower GroundVCGNDNCDescriptionThis pin is the Error Amplifier output and is made available for loop compensation.This is the inverting input of the Error Amplifier. It is normally connected to the switching powersupply output through a resistor divider.A voltage proportional to inductor current is connected to this input. The PWM uses thisinformation to terminate the output switch conduction.The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistorRT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible.This pin is the combined control circuitry and power ground.This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourcedand sunk by this pin. The output switches at one−half the oscillator frequency.This pin is the positive supply of the control IC.This is the reference output. It provides charging current for capacitor CT through resistor RT.This pin is a separate power ground return that is connected back to the power source. It is usedto reduce the effects of switching transient noise on the control circuitry.The Output high state (VOH) is set by the voltage applied to this pin. With a separate power sourceconnection, it can reduce the effects of switching transient noise on the control circuitry.This pin is the control circuitry ground return and is connected back to the powersource ground.No connection. These pins are not internally connected.http://onsemi.com

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UC3844B, UC3845B, UC2844B, UC2845B

OPERATING DESCRIPTION

The UC3844B, UC3845B series are high performance,fixed frequency, current mode controllers. They arespecifically designed for Off−Line and dc−dc converterapplications offering the designer a cost−effective solutionwith minimal external components. A representative blockdiagram is shown in Figure 16.

Oscillator

The oscillator frequency is programmed by the valuesselected for the timing components RT and CT. Capacitor CTis charged from the 5.0 V reference through resistor RT toapproximately 2.8 V and discharged to 1.2 V by an internalcurrent sink. During the discharge of CT, the oscillatorgenerates an internal blanking pulse that holds the centerinput of the NOR gate high. This causes the Output to be ina low state, thus producing a controlled amount of outputdeadtime. An internal flip−flop has been incorporated in theUCX844/5B which blanks the output off every other clockcycle by holding one of the inputs of the NOR gate high. Thisin combination with the CT discharge period yields outputdeadtimes programmable from 50% to 70%. Figure 2 showsRT versus Oscillator Frequency and Figure 3, OutputDeadtime versus Frequency, both for given values of CT.Note that many values of RT and CT will give the sameoscillator frequency but only one combination will yield aspecific output deadtime at a given frequency. The oscillatorthresholds are temperature compensated to within ±6% at 50 kHz. Also, because of industry trends moving theUC384X into higher and higher frequency applications, theUC384XB is guaranteed to within ±10% at 250 kHz.

In many noise−sensitive applications it may be desirableto frequency−lock the converter to an external system clock.This can be accomplished by applying a clock signal to thecircuit shown in Figure 18. For reliable locking, thefree−running oscillator frequency should be set about 10%less than the clock frequency. A method for multi−unitsynchronization is shown in Figure 19. By tailoring theclock waveform, accurate Output duty cycle clamping canbe achieved to realize output deadtimes of greater than 70%.

Error Amplifier

Comparator. This guarantees that no drive pulses appear atthe Output (Pin 6) when Pin 1 is at its lowest state (VOL).This occurs when the power supply is operating and the loadis removed, or at the beginning of a soft−start interval(Figures 21, 22). The Error Amp minimum feedbackresistance is limited by the amplifier’s source current(0.5 mA) and the required output voltage (VOH) to reach thecomparator’s 1.0 V clamp level:

Rf(min) ≈

3.0 (1.0 V) + 1.4 V

= 8800 W

0.5 mA

Current Sense Comparator and PWM Latch

The UC3844B, UC3845B operate as a current modecontroller, whereby output switch conduction is initiated bythe oscillator and terminated when the peak inductor currentreaches the threshold level established by the ErrorAmplifier Output/Compensation (Pin 1). Thus the errorsignal controls the peak inductor current on acycle−by−cycle basis. The Current Sense Comparator PWMLatch configuration used ensures that only a single pulseappears at the Output during any given oscillator cycle. Theinductor current is converted to a voltage by inserting theground−referenced sense resistor RS in series with thesource of output switch Q1. This voltage is monitored by theCurrent Sense Input (Pin 3) and compared to a level derivedfrom the Error Amp Output. The peak inductor current undernormal operating conditions is controlled by the voltage atPin 1 where:

Ipk =

V(Pin 1) − 1.4 V

3 RS

Abnormal operating conditions occur when the powersupply output is overloaded or if output voltage sensing islost. Under these conditions, the Current Sense Comparatorthreshold will be internally clamped to 1.0 V. Therefore themaximum peak switch current is:

Ipk(max) =

1.0 VRS

A fully compensated Error Amplifier with access to theinverting input and output is provided. It features a typicaldc voltage gain of 90 dB, and a unity gain bandwidth of1.0 MHz with 57 degrees of phase margin (Figure 6). Thenon−inverting input is internally biased at 2.5 V and is notpinned out. The converter output voltage is typically divideddown and monitored by the inverting input. The maximuminput bias current is −2.0 mA which can cause an outputvoltage error that is equal to the product of the input biascurrent and the equivalent input divider source resistance.The Error Amp Output (Pin 1) is provided for externalloop compensation (Figure 29). The output voltage is offsetby two diode drops (≈1.4 V) and divided by three before itconnects to the inverting input of the Current Sense

When designing a high power switching regulator itbecomes desirable to reduce the internal clamp voltage in orderto keep the power dissipation of RS to a reasonable level. Asimple method to adjust this voltage is shown in Figure 20. Thetwo external diodes are used to compensate the internal diodes,yielding a constant clamp voltage over temperature. Erraticoperation due to noise pickup can result if there is an excessivereduction of the Ipk(max) clamp voltage.

A narrow spike on the leading edge of the currentwaveform can usually be observed and may cause the powersupply to exhibit an instability when the output is lightlyloaded. This spike is due to the power transformerinterwinding capacitance and output rectifier recovery time.The addition of an RC filter on the Current Sense Input witha time constant that approximates the spike duration willusually eliminate the instability (refer to Figure 24).

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UC3844B, UC3845B, UC2844B, UC2845B

VCCVinVCC 7(12)36VReferenceRegulatorR2.5VROscillatorCT4(7)+1.0mA2RRErrorAmplifierR1.0VCurrent SenseComparatorGND 5(9)Vref8(14)RTInternalBias3.6VVCCUVLO+−VrefUVLO+−(SeeText)VC7(11)Output6(10)Q1SQPWMLatchVoltageFeedbackInput2(3)Output/Compensation1(1)Power Ground5(8)Current Sense Input3(5)RSPin numbers adjacent to terminals are for the 8−pin dual−in−line package.Pin numbers in parenthesis are for the D suffix SOIC−14 package.= Sink Only Positive True LogicFigure 16. Representative Block DiagramCapacitor CT

Latch 󰁑Set\" InputOutput/

CompensationCurrent SenseInputLatch 󰁑Reset\"Input

Output

Large RT/Small CT

Small RT/Large CT

Figure 17. Timing Diagram

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UC3844B, UC3845B, UC2844B, UC2845B

Undervoltage Lockout

Two undervoltage lockout comparators have beenincorporated to guarantee that the IC is fully functionalbefore the output stage is enabled. The positive powersupply terminal (VCC) and the reference output (Vref) areeach monitored by separate comparators. Each has built−inhysteresis to prevent erratic output behavior as theirrespective thresholds are crossed. The VCC comparatorupper and lower thresholds are 16 V/10 V for the UCX844B,and 8.4 V/7.6 V for the UCX845B. The Vref comparatorupper and lower thresholds are 3.6 V/3.4 V. The largehysteresis and low startup current of the UCX844B makesit ideally suited in off−line converter applications whereefficient bootstrap startup techniques are required(Figure 30). The UCX845B is intended for lower voltagedc−dc converter applications. A 36 V Zener is connected asa shunt regulator from VCC to ground. Its purpose is toprotect the IC from excessive voltage that can occur duringsystem startup. The minimum operating voltage for theUCX844B is 11 V and 8.2 V for the UCX845B.

Output

designer added flexibility in tailoring the drive voltageindependent of VCC. A Zener clamp is typically connectedto this input when driving power MOSFETs in systemswhere VCC is greater than 20 V. Figure 23 shows properpower and control ground connections in a current−sensingpower MOSFET application.

Reference

The 5.0 V bandgap reference is trimmed to ±1.0%tolerance at TJ = 25°C on the UC284XB, and ±2.0% on theUC384XB. Its primary purpose is to supply charging currentto the oscillator timing capacitor. The reference hasshort−circuit protection and is capable of providing inexcess of 20 mA for powering additional control systemcircuitry.

Design Considerations

These devices contain a single totem pole output stage thatwas specifically designed for direct drive of powerMOSFETs. It is capable of up to ±1.0 A peak drive currentand has a typical rise and fall time of 50 ns with a 1.0 nF load.Additional internal circuitry has been added to keep theOutput in a sinking mode whenever an undervoltage lockoutis active. This characteristic eliminates the need for anexternal pulldown resistor.

The SOIC−14 surface mount package provides separatepins for VC (output supply) and Power Ground. Properimplementation will significantly reduce the level ofswitching transient noise imposed on the control circuitry.This becomes particularly useful when reducing the Ipk(max)clamp level. The separate VC supply input allows the

Do not attempt to construct the converter onwire−wrap or plug−in prototype boards. High frequencycircuit layout techniques are imperative to preventpulse−width jitter. This is usually caused by excessive noisepick−up imposed on the Current Sense or Voltage Feedbackinputs. Noise immunity can be improved by lowering circuitimpedances at these points. The printed circuit layout shouldcontain a ground plane with low−current signal andhigh−current switch and output grounds returning onseparate paths back to the input filter capacitor. Ceramicbypass capacitors (0.1 mF) connected directly to VCC, VC,and Vref may be required depending upon circuit layout.This provides a low impedance path for filtering the highfrequency noise. All high current loops should be kept asshort as possible using heavy copper runs to minimizeradiated EMI. The Error Amp compensation circuitry andthe converter output voltage divider should be located closeto the IC and as far as possible from the power switch andother noise−generating components.

Vref8(14)RTRBiasRRB6OscCT0.01ExternalSyncInput

EA4(7)+2R472(3)RC525.0k15(9)5.0kRQS4(7)72(3)EA+2RRRA85.0k43OscR8(14)RBiasMC14551(1)1(1)To AdditionalUCX84XBs5(9)The diode clamp is required if the Sync amplitude is large enough to causethe bottom side of CT to go more than 300 mV below ground.

f󰀃+󰀃

1.44(RA󰀃)󰀃2RB)CRAD(max)󰀃+󰀃

RA󰀃)󰀃2RB

Figure 18. External Clock Synchronization

Figure 19. External Duty Cycle Clamp and

Multi−Unit Synchronization

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UC3844B, UC3845B, UC2844B, UC2845B

VCC7(12)5.0V Ref5.0V Ref8(14)RBiasR+−Osc4(7)R2EA+1.0 mA2(3)2RRVClampSQR1.0VComp/Latch3(5)5(9)Vin8(14)+−7(11)Q1T6(10)2(3)5(8)1.0M1(1)RSCRBiasR+−Osc+1.0mA2RR1.0VSQRT4(7)EAR11(1)VClamp ≈ǒ1.67+ 0.33x10−3R2)1R1Ǔ1R2ǓWhere: 0 ≤ VClamp ≤ 1.0 VǒR1R)R2VIpk(max)󰀃[󰀃ClampRStSoft−Start ≈ 3600C in mF5(9)Figure 20. Adjustable Reduction of Clamp LevelFigure 21. Soft−Start CircuitVCC7(12)Vin(12)VCCVinVPin󰀃5󰀃[󰀃RS󰀃Ipk󰀃rDS(on)rDM(on)󰀃)󰀃RSIf: SENSEFET=MTP10N10MRS= 2005.0V Ref8(14)RBiasR+−Osc4(7)+1.0 mA2(3)R21(1)R1MPSA635(9)5.0V Ref+−7(11)Q1TSQR5(8)6(10)SQRComp/Latch3(5)RSControl Circuitry Ground:To Pin (9)(5)RS1/4 W(8)T(10)+−+−(11)GMThen:󰀃VPin󰀃5󰀃[󰀃0.075󰀃IpkDSENSEFETSKVClampEA2RR1.0VComp/LatchPower Ground:To Input SourceReturnVClamp ≈ǒ1.67R2)1R1ǓWhere: 0 ≤ VClamp ≤ 1.0 VtSoft-Start+*In1*󰀃VC󰀃CR1󰀃R2R1)R23VClampƪƫVIpk(max)󰀃[󰀃ClampRSVirtually lossless current sensing can be achieved with the implementationof a SENSEFETt power switch. For proper operation during over−currentconditions, a reduction of the Ipk(max) clamp level must be implemented.Refer to Figures 20 and 22.Figure 22. Adjustable Buffered Reduction of

Clamp Level with Soft−Start

Figure 23. Current Sensing Power MOSFET

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11

UC3844B, UC3845B, UC2844B, UC2845B

VCC7(12)Vin5.0V Ref+−+−TSQRComp/Latch3(5)CRRS6(10)5(8)7(11)Q1The addition of the RC filter will eliminateinstability caused by the leading edge spike on the current waveform.Figure 24. Current Waveform Spike Suppression

VCC7(12)Vin+0IBVin

Base ChargeRemovalC15.0V Ref+−+−TSQRComp/Latch3(5)RS5(8)7(11)Rg6(10)Q1−Q16(10)5(8)3(5)RS

Series gate resistor Rg will damp any high frequencyparasitic oscillations caused by the MOSFET inputcapacitance and any series wiring inductance in thegate−source circuit.

The totem pole output can furnish negative base currentfor enhanced transistor turn−off, with the addition ofcapacitor C1.

Figure 25. MOSFET Parasitic OscillationsFigure 26. Bipolar Transistor Drive

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12

UC3844B, UC3845B, UC2844B, UC2845B

VCC7(12)IsolationBoundary5.0V Ref+−+−TSQRComp/Latch3(5)CRRSNSNP7(11)Q1+0−6(10)5(8)50% DCVGS Waveforms+0−25% DCVinIpk =V(Pin󰀃1) − 1.43 RSSǓǒNNpFigure 27. Isolated MOSFET Drive8(14)RBiasROsc4(7)+1.0 mA2(3)2RREA1(1)MCR1012N39052N39035(9)The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). Thesimple two transistor circuit can be used in place of the SCR as shown. Allresistors are 10 k.Figure 28. Latched ShutdownFrom VORiRdCf2.5V+1.0mA2(3)Rf1(1)EA2RRFrom VORpCp2.5V+2(3)RdCfRf1(1)EA1.0mA2RRRiRf ≥ 8.8k5(9)5(9)Error Amp compensation circuit for stabilizing any current mode topology exceptfor boost and flyback converters operating with continuous inductor current.Error Amp compensation circuit for stabilizing current mode boostand flyback topologies operating with continuous inductor current.

Figure 29. Error Amplifier Compensation

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13

UC3844B, UC3845B, UC2844B, UC2845B

MBR16354.7W115 VacMDA202+L125056k4.7k3300pF1N4935+T12200MUR110+1000+5.0V/4.0A

5.0V RTN

1N49357(12)+681000471000MUR110+L210+12V/0.3A

1005.0V Ref0.018(14)33kRBiasROsc1.0nF18k100pF4(7)2(3)150k1(1) 5(9)±12V RTN

+−7(11)1N4937+10L3+−12V/0.3A

+−+SRTQ226(10)1N5819MTP4N50680pF2.7k1N4937EA5(8)1.0k3(5)470pF0.54.7kComp/LatchT1 −Primary: 45 Turns #26 AWG

Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar WoundSecondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound

Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar WoundCore: Ferroxcube EC35−3C8Bobbin: Ferroxcube EC35PCB1

Gap: ≈ 0.10\" for a primary inductance of 1.0 mH

L1− 15 mH at 5.0 A, Coilcraft Z7156L2, L3− 25 mH at 5.0 A, Coilcraft Z7157

Figure 30. 7 W Off−Line Flyback Regulator

TestLine Regulation:5.0V±12VConditionsVin = 95 Vac to 130 VacVin = 115 Vac, Iout = 1.0 A to 4.0 AVin = 115 Vac, Iout = 100 mA to 300 mAVin = 115 VacVin = 115 VacResultsD = 50 mV or ±0.5%D = 24 mV or ±0.1%D = 300 mV or ±3.0%D = 60 mV or ±0.25%40 mVpp80 mVpp70%Load Regulation:5.0V±12VOutput Ripple:Efficiency5.0V±12VAll outputs are at nominal load currents unless otherwise noted.

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14

UC3844B, UC3845B, UC2844B, UC2845B

Vin = 15VUC3845B 7(12)Output Load Regulation(Open Loop Configuration)+IO (mA)47VO (V)29.928.828.327.424.48(14)10kReferenceRegulator2.5VRRInternalBias3.6V34VVCC+UVLO−7(11)1N581902918361N5819+−VrefUVLO6(10)T15101.0nF4(7)2(3)ErrorAmplifier1(1)Osc+0.5mA2RR1.0VSR+5(8)PWMLatch3(5)Connect toPin 2 forclosed loopoperation.R2VO ≈ 2 (Vin)+47QCurrent SenseComparator5(9)VO = 2.5R1ǒR2)1ǓR1The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistormay be required when using tantalum or other low ESR capacitors. The converter’s output can provide excellent lineand load regulation by connecting the R2/R1 resistor divider as shown.Figure 31. Step−Up Charge Pump ConverterVin = 15VUC3845B 7(12)Output Load Regulation+47IO (mA)02918321N5819VO (V)−14.4−13.2−12.5−11.7−10.6VO ≈ −Vin8(14)10k2.5VRRInternalBias3.6VReferenceRegulator34VVCCUVLO+−7(11)+−VrefUVLOT6(10)15101.0nF4(7)2(3)ErrorAmplifier1(1)Osc+0.5mA2RR1.0VSR1N58195(8)PWMLatch3(5)+47QCurrent SenseComparator5(9)The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A.

An additional series resistor may be required when using tantalum or other low ESR capacitors.

Figure 32. Voltage−Inverting Charge Pump Converter

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15

UC3844B, UC3845B, UC2844B, UC2845B

MARKING DIAGRAMS

PDIP−8N SUFFIXCASE 626

8

UC384xBN AWL YYWW1

8

UC3844BVN AWL YYWW1

8

UC3845BVN FAWL YYWW1

8

UC2844BN FAWL YYWW1

SOIC−8D1 SUFFIXCASE 751

8384xBALYW1

8384xBALYWV1

18284xBALYW

SOIC−14D SUFFIXCASE 751A

14

UC384xBDAWLYWW1

114

UC384xBVDAWLYWW

114

UC284xBDAWLYWW

xFAWL, LYY, YWW, W= 4 or 5

= Wafer Fab

= Assembly Location= Wafer Lot= Year

= Work Week

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16

UC3844B, UC3845B, UC2844B, UC2845B

PACKAGE DIMENSIONS

PDIP−8N SUFFIXCASE 626−05ISSUE L

NOTES:

1.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.

2.PACKAGE CONTOUR OPTIONAL (ROUND ORSQUARE CORNERS).

3.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.

DIMABCDFGHJKLMNMILLIMETERSMINMAX9.4010.166.106.603.944.450.380.511.021.782.54 BSC0.761.270.200.302.923.437.62 BSC−−−10 _0.761.01INCHESMINMAX0.3700.4000.2400.2600.1550.1750.0150.0200.0400.0700.100 BSC0.0300.0500.0080.0120.1150.1350.300 BSC−−−10 _0.0300.04085−B−14FNOTE 2−A−LC−T−SEATINGPLANEJNDKMMTAMHG0.13 (0.005)BMhttp://onsemi.com

17

UC3844B, UC3845B, UC2844B, UC2845B

PACKAGE DIMENSIONS

SOIC−8D1 SUFFIXCASE 751−07ISSUE AC

NOTES:

1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDEMOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6.751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

MILLIMETERSMINMAX4.805.003.804.001.351.750.330.511.27 BSC0.100.250.190.250.401.270 _8 _0.250.505.806.20

INCHES

MINMAX0.10.1970.1500.1570.0530.0690.0130.0200.050 BSC0.0040.0100.0070.0100.0160.0500 _8 _0.0100.0200.2280.244

−X−A85B1S40.25 (0.010)MYM−Y−GKC−Z−HD0.25 (0.010)

MSEATINGPLANENX 45_0.10 (0.004)MJZY

SX

SDIMABCDGHJKMNS

SOLDERING FOOTPRINT*

1.520.0607.00.2754.00.1550.60.0241.2700.050SCALE 6:1

mmǓǒinches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

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18

UC3844B, UC3845B, UC2844B, UC2845B

PACKAGE DIMENSIONS

SOIC−14D SUFFIXCASE 751A−03ISSUE G

−A−148−B−P7 PL0.25 (0.010)MBM17GC−T−SEATINGPLANERX 45_FNOTES:1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDEDAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.127(0.005) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIALCONDITION.

DIMABCDFGJKMPR

MILLIMETERSMINMAX8.558.753.804.001.351.750.350.490.401.251.27 BSC0.190.250.100.250 7 __5.806.200.250.50

INCHES

MINMAX0.3370.3440.1500.1570.0540.0680.0140.0190.0160.0490.050 BSC0.0080.0090.0040.0090 7 __0.2280.2440.0100.019

D14 PL0.25 (0.010)MKTBSMASJhttp://onsemi.com

19

UC3844B, UC3845B, UC2844B, UC2845B

SENSEFET is a trademark of Semiconductor Components Industries, LLC.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll FreeUSA/CanadaJapan: ON Semiconductor, Japan Customer Focus Center2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051Phone: 81−3−5773−3850http://onsemi.com20UC3844B/D